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liuyz
Adventurer
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Registered: ‎01-13-2019

Is U250 PCIe in full duplex mode?

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Hi, I'm evaluating the Alveo U250 card, and my workflow is using OpenCL in SDAccel IDE.

As asked in the subject title,

1/ is the card hardware suport full duplex mode?

2/ is the OpenCL BSP/shell suport the full duplex mode?

3/ if it is suported, do I have to manually enable this? or it is available automatically through the runtime env?

Thanks a lot.

 

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @liuyz,

For the hardware side, the PCIe protocol allows concurrent transfer, as do the PCI Express DMA cores available.  Host-to-card and Card-to-Host data transfers can run concurrently once descriptors are made available for both.

Within the Shell/SDAccel framework - it looks like host code scheduling would allow concurrent data transfer, with careful architecture around multiple threads and the memory accesses.  The OpenCL and host codes for data transfer using SDAccel kernels is discussed in detail here: https://www.xilinx.com/html_docs/xilinx2018_3/sdaccel_doc/vpy1519742402284.html#vpy1519742402284 in the SDAccel Environment Guide for 2018.3.

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @liuyz,

 

Can you provide more information?  I am confused by your reference to PCIe and Full Duplex.  Those terms are not typically used together...

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liuyz
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@bethe wrote:

Hi @liuyz,

 

Can you provide more information?  I am confused by your reference to PCIe and Full Duplex.  Those terms are not typically used together...


Hi Bethe,

I mean the DMA data transfer between the host and the FPGA via PCIe interface.

Could you help to clarify how full duplex is supported on the board hardware and the OpenCL BSP/shell, seperately?

Thanks a lot.

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @liuyz,

The Alveo U250 card features a Gen3 x16 bidriectional PCI Express link.  The DMA engine provided by the Shell handles the data transfer both in the Host-to-Card and Card-to-Host direction - and the Xilinx Runtime Environment contains the PCIe drivers.  Via the SDAccel Environment, the developer would create OpenCL kernels that utilize data connecttions to the provided shell, which then does the PCIe transfers.

For more information on the Shell and SDAccel environment, please review: https://www.xilinx.com/html_docs/accelerator_cards/alveo_doc/index.html and additionally: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html#documentation. 

For more information on the Hardware itself, the User Guide can be found at https://www.xilinx.com/products/boards-and-kits/alveo/u250.html#documentation, and reference UG1289

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liuyz
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Hi @bethe ,

Thanks for the explaination.

For the host-to-card and card-to-host transfer in DMA engine, are they able to transfer concurrently in both directions (full duplex)? Both hardware level and BSP level.

We have current design based on Intel/Altera cards, and condering an evaluation on Xilinx card. Knowing this details can greatly help us do our estimation and budgeting.

Thanks a lot.

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bethe
Xilinx Employee
Xilinx Employee
1,101 Views
Registered: ‎12-10-2013

Hi @liuyz,

For the hardware side, the PCIe protocol allows concurrent transfer, as do the PCI Express DMA cores available.  Host-to-card and Card-to-Host data transfers can run concurrently once descriptors are made available for both.

Within the Shell/SDAccel framework - it looks like host code scheduling would allow concurrent data transfer, with careful architecture around multiple threads and the memory accesses.  The OpenCL and host codes for data transfer using SDAccel kernels is discussed in detail here: https://www.xilinx.com/html_docs/xilinx2018_3/sdaccel_doc/vpy1519742402284.html#vpy1519742402284 in the SDAccel Environment Guide for 2018.3.

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liuyz
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Registered: ‎01-13-2019
Thanks for conformation.
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