cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
221 Views
Registered: ‎01-08-2020

Issue in identifying the DDR address locations

 
            I have a small issue regarding the data transfers from host to four DDR banks . In the process of exploring Vadd example I have come across the  data transfers from HOST to DDR banks but to transfer the data from host to DDR and read the data to host from DDR we require specific DDR's address location . My issue is that I'm unable to find out to which specific address location of DDR's is being accessed by HOST, hence   I require the  address locations  of DDR's which I'm unable to figure it out. Is there any way of knowing the address locations of DDR banks. Please let me know.
 
Thanks & Regards,
Prashanth.  
0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
152 Views
Registered: ‎10-19-2015

Re: Issue in identifying the DDR address locations

Hi @mdpuma 

OpenCL/C++ runtime libraries, V++, and Vitis should be handling a lot of that for you. 

For example, you would just need to create a buffer and the underlying stack would know that buffer goes into DDR. 

What are you specifically trying to do? 

Did you see any direct address coding in the Vadd example? 

Maybe this other post could help you: https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/How-to-make-a-buffer-stay-in-global-memory/m-p/1004993

Regards,

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
129 Views
Registered: ‎01-08-2020

Re: Issue in identifying the DDR address locations

Hi @mcertosi 

No , i did not find any direct address coding in vadd example.

I have done two experiments in mapping of vadd kernel to DDR.

1 . Mapping of kernel to one DDR (this mapping is done by writting a seperate  connectivity.sp script in a config.ini file, by default it maps to single DDR )

12.png

In the above example system diagram,  how can i assume that the data is filling in the base address of first DDR?

2 . Mapping of kernel to Three DDRs ..

 

Screenshot from 2020-02-12 12-47-00.png

In profile summary of  vitis analyzer, I have found base address of all the DDR banks . Screenshot from 2020-02-12 12-50-12.png

For now , I'm assuming that the above data filling is happening in the base addresses of DDR banks. If i want to fill the data from host to the particular DDR address location like base address + offset ( ex: 0x40_0000_0000 + offset adress) or to read  the data from particular address locations of DDR to host , how can I proceed ? Please give me some insights on this. 

Regards,

Prashanth.

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
84 Views
Registered: ‎10-19-2015

Re: Issue in identifying the DDR address locations

Hi @mdpuma 

Could you give me more information on your methodology for creating the design?

Usually you would have a kernel (.xo) and you can link it to DDR using a V++ switch like --sp. This wouldn't require you to do the direct address mapping yourself. Then you can stay in the Vitis acceleration flow. 

Then you can use the OpenCL and the "buffer transfer" section of the documentation below 

https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk560402095.html?hl=memory%2Ctransfer

Otherwise I'm not clear on what you are asking. 

Regards,

M

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos