02-05-2020 11:05 PM
02-11-2020 12:14 PM
OpenCL/C++ runtime libraries, V++, and Vitis should be handling a lot of that for you.
For example, you would just need to create a buffer and the underlying stack would know that buffer goes into DDR.
What are you specifically trying to do?
Did you see any direct address coding in the Vadd example?
Maybe this other post could help you: https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/How-to-make-a-buffer-stay-in-global-memory/m-p/1004993
02-11-2020 11:31 PM
No , i did not find any direct address coding in vadd example.
I have done two experiments in mapping of vadd kernel to DDR.
1 . Mapping of kernel to one DDR (this mapping is done by writting a seperate connectivity.sp script in a config.ini file, by default it maps to single DDR )
In the above example system diagram, how can i assume that the data is filling in the base address of first DDR?
2 . Mapping of kernel to Three DDRs ..
In profile summary of vitis analyzer, I have found base address of all the DDR banks .
For now , I'm assuming that the above data filling is happening in the base addresses of DDR banks. If i want to fill the data from host to the particular DDR address location like base address + offset ( ex: 0x40_0000_0000 + offset adress) or to read the data from particular address locations of DDR to host , how can I proceed ? Please give me some insights on this.
02-13-2020 02:16 PM
Could you give me more information on your methodology for creating the design?
Usually you would have a kernel (.xo) and you can link it to DDR using a V++ switch like --sp. This wouldn't require you to do the direct address mapping yourself. Then you can stay in the Vitis acceleration flow.
Then you can use the OpenCL and the "buffer transfer" section of the documentation below
Otherwise I'm not clear on what you are asking.