cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
dharpeer
Adventurer
Adventurer
458 Views
Registered: ‎11-24-2020

Overclocking FPGA

Jump to solution

Hi,

Can I know the benefits and limitations of over clocking an FPGA?

(I suppose the way to do this would be through a MMCM ?)

 

Thanks in Advance!

Tags (1)
0 Kudos
Reply
1 Solution

Accepted Solutions
avrumw
Guide
Guide
343 Views
Registered: ‎01-23-2009
7 Replies
dpaul24
Scholar
Scholar
447 Views
Registered: ‎08-07-2014

@dharpeer ,

"over clocking" is a term more applied to ASICs. You can always play around with the clock rate of your design when implemented on a FPGA.

You can change the clock rate by changing the clock freq which the main MMCM outputs, but that might result in the design having timing errors which would lead to erroneous operation of the design implemented in the FPGA.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
Reply
drjohnsmith
Teacher
Teacher
435 Views
Registered: ‎07-09-2009

in general, clocking FPGAs outside there data sheet limits is not done,

My guess is that they are so dammed expensive compared to CPU's , and  a lot more specialised, 

    so lees of them around in the community,

Any tests you do would be of interest.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Reply
dharpeer
Adventurer
Adventurer
415 Views
Registered: ‎11-24-2020
0 Kudos
Reply
joancab
Scholar
Scholar
403 Views
Registered: ‎05-11-2015

Overclocking is more a CPU hackers term. Imo, it makes little sense for FPGA, especially because there are usually a number of clocks. I suppose it means using clocks faster than what is considered safe.

Simply: don't do that. For data to be correct you need to respect some timing restrictions that indirectly set you maximum frequency. If you simply ignore that and use a faster clock you will simply have wrong data and/or registers in metastable states. In short: something useless, except as a coffee cup heater.

If you want faster data processing, the way to go is to carefully study the process and optimize it for speed and/or paralleling and pipelining. These are the educated and proven ways for high speed on FPGA.

0 Kudos
Reply
richardhead
Scholar
Scholar
396 Views
Registered: ‎08-01-2012

@dharpeer What is your end goal?

A design on an FPGA will have been built and then had the timing analysed using known timing models. If the "passes", then a design will work at the specified clock speed. It may work fine with a faster clock but may not. But two designs are not the same. One may work at 200Mhz, while another on the same FPGA times fine at 300Mhz. So why are you talking about overclocking? no two designs are the same.

0 Kudos
Reply
dpaul24
Scholar
Scholar
394 Views
Registered: ‎08-07-2014

@dharpeer ,

You should consider the questions other members have posted!

Referring to the thread you have referred, it is a very old post. After reading avrum's answer in that post post, I see no way how it relates to overclocking (maybe you do not interpret it in the way I am doing it).

A design implemented in an FPGA can be overclocked any time. The max clock that can be set depends upon the MMCM output restrictions, the clock buffers and the clock-tree structure used inside the FPGA fabric. Whether the design will work or not at the changed clocked speed, is a different issue.

 

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

avrumw
Guide
Guide
344 Views
Registered: ‎01-23-2009