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jurybadulin
Newbie
Newbie
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Registered: ‎11-27-2018

QSFP IIC registers and GPIO pins on Alveo U280

Hi,

I am using U280 in Custom Board Flow mode. The first target in my development is to make NIC card exploiting XDMA and 100G Ethernet Subsystem functionality. For some reason Vitis Flow is not acceptable for me. To turn on network function I need to control at least QSFP GPIO pins (ModSelL,ResetL, etc. ...) and to control QSFP IIC registers. UG1314 v1.4 p 9 shows that IIC on the u280 board is controlled by Satellite Controller and QSFP GPIO pins are controlled through I/O expander. The question is - how to get access form FPGA to Satellite controller to program I/O expander and to read/write QSFP internal registers? Is there a known documented way to perform this action?

Regards,

Jury Badulin

 

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JohnFedakIV
Moderator
Moderator
180 Views
Registered: ‎09-04-2020

Hi @jurybadulin ,

Welcome to the Xilinx forums!

Please see this post for a similar discussion:

https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/QSFP-I2C-access-on-U50-and-U280/td-p/1123205

Currently, there isn't a way for the FPGA to control the QSFP GPIO or access the QSFP registers through the CMS/SC.

Regards,
~John

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