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jpbb
Participant
Participant
1,188 Views
Registered: ‎03-26-2018

U200: need help for mapping GT quads

Hi,

we have today successfully implemented an aurora link with the configuration shown below.Screenshot from 2020-04-02 09-45-38.png

We use a special DAC (Direct Attach Cable QSFP28 <-> 4 SFP, passive copper cable.) allowing to connect the u200 to a zcu111 board. It works fine. 

I need now to connect this system to another board which has an onboard lase TX/RX module. I therefrore need to use a optical fiber, and a sfp optical module which I plugged into a mechanical adapter(QSFP28 to QSFP)  (https://www.amazon.in/Mellanox-Technologies-MAM1Q00A-QSA-CABLE-ADAPTER/dp/B00FFVFVS0).

placed in the Alveo QSFP28 port.

Here are the questions:

  • Could anyone give us a map how to use the GTquad and GT lane? How are they connected to qsfp0_rx/tx1,2,3,4 ?
  • Do I need to do anything special when using a laser module instead of the copper link? I disconnected low_power mode but I do not have channel/lane up indications. 

Any help is welcome.

Thanks in advance!

JP

 

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mcertosi
Xilinx Employee
Xilinx Employee
1,150 Views
Registered: ‎10-19-2015

Hi @jpbb 

There have been many posts on the forums asking about qsfp usage. You might want to search around here. 

Here's a Xilinx answer record. https://www.xilinx.com/support/answers/71981.html it describes how to use the board aware flow with the Alveo cards. The board aware flow will connect the GTs to the proper quads for use with the QSFP ports. Aurora is not listed as a supported configuration though. 

Do not use an XDC, I do not believe the published ones are correct for the u200 and u250. 

I think LPMODE should be low, you might need to connect external power. However I'm hoping that the board aware flow can get your GT link up.

Regards,

M

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jpbb
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Registered: ‎03-26-2018

Hi Mcertosi

As you know form earlier discussions, we are working directly with IPI.... but I am very disappointed that Xilinx does not make the efforts to correct the xdc files....especially when, we, customers, do noyt have access to the hardware descriptions (schematics and so on).

Cheers.

JP

 

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mcertosi
Xilinx Employee
Xilinx Employee
1,079 Views
Registered: ‎10-19-2015

Hi @jpbb,

We are still working on correcting them. They are currently wrong though. 

The status is "in progress" but there is no timeline associated. 

Not sure if it helps, but we did recently do a full revamp of the U280 and U50 XDCs, though they are not applicable to the u200 and u250. 

I'm sending your feedback up my management chain. 

Regards,

M

 

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jpbb
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Registered: ‎03-26-2018

Thanks for the feed back. I will wait for the released version.

//JP

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