05-14-2020 10:35 PM
Recently , I instantiated a pcie endpoint Ip using IP catlog, but after successfully gengerating the bit files and download it into U200 ，The Computer couldn't find the PCIE！ The constraint I used is from XILINX.COM and the synthesis tools is VIVADO2019.1 。When I restart the computer ,The default version that download by xilinx can work well. So, I dont't know where the problem is ?
05-21-2020 10:12 AM
How are you generating the PCIe block?
You should be using IPI and the board aware flow, this should contain all the constraints necessary for you.
Since the shell provided from Xilinx works, but your custom one doesn't the problem is somewhere in the configuration of your IP.