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vconst89
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Registered: ‎09-10-2020

U50 Card, XOCL PCIe resources

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Hi ,

Is it possible to get a bit more information about PCIe memory resources available with U50 standard shell? What each of these ranges is used for? 

$ lspci -s 17:00.1 -nn -v

17:00.1 Processing accelerators [1200]: Xilinx Corporation Device [10ee:5021]
Subsystem: Xilinx Corporation Device [10ee:000e]
Flags: bus master, fast devsel, latency 0, IRQ 69, NUMA node 0
Memory at 380070000000 (64-bit, prefetchable) [size=32M]
Memory at 380074000000 (64-bit, prefetchable) [size=128K]
Memory at 380060000000 (64-bit, prefetchable) [size=256M]
Capabilities: <access denied>
Kernel driver in use: xocl
Kernel modules: xocl

This document didn't help me, but probably I've been reading the wrong chapters   https://xilinx.github.io/XRT/2018.3/html/xocl_ioctl.main.html 

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vconst89
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Registered: ‎09-10-2020

https://xilinx.github.io/XRT/master/html/security.html#pcie-topology

PCIe Topology

As mentioned before Alveo platforms have two physical function architecture where each function has its own BARs. The table below gives overview of the topology and functionality.

PFBARDriverPurpose

0

0

xclmgmt

Memory mapped access to privileged IPs in the shell as shown in the Figure above.

0

2

xclmgmt

Setup MSI-X vector table

1

0

xocl

Access to register maps of user compiled compute units in the DFX region

1

2

xocl

Memory mapped access to XDMA/QDMA PCIe DMA engine programming registers

1

4

xocl

CPU direct and P2P access to device attached DDR/HBM/PL-RAM memory. By default its size is limited to 256MB but can be expanded using XRT xbutil tool as described in PCIe Peer-to-Peer (P2P)

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vconst89
Adventurer
Adventurer
238 Views
Registered: ‎09-10-2020

https://xilinx.github.io/XRT/master/html/security.html#pcie-topology

PCIe Topology

As mentioned before Alveo platforms have two physical function architecture where each function has its own BARs. The table below gives overview of the topology and functionality.

PFBARDriverPurpose

0

0

xclmgmt

Memory mapped access to privileged IPs in the shell as shown in the Figure above.

0

2

xclmgmt

Setup MSI-X vector table

1

0

xocl

Access to register maps of user compiled compute units in the DFX region

1

2

xocl

Memory mapped access to XDMA/QDMA PCIe DMA engine programming registers

1

4

xocl

CPU direct and P2P access to device attached DDR/HBM/PL-RAM memory. By default its size is limited to 256MB but can be expanded using XRT xbutil tool as described in PCIe Peer-to-Peer (P2P)

View solution in original post