Hi @Quxm ,
There are two ways to do RTL in the Alveo accelerator cards.
1. Using RTL Kernels with the provided shell in Vitis, the shell will have a built-in PCIe DMA and communication to the Satellite Controller which monitors the board's power and temperature. This works with XRT (https://xilinx.github.io/XRT/master/html/index.html) to communicate with the host, debug the board, and load different configurations.
A good tutorial is found here:
https://github.com/Xilinx/Vitis-Tutorials/blob/master/Hardware_Accelerators/Feature_Tutorials/01-rtl_kernel_workflow/README.md
The Vitis documentation for RTL Kernels is found here:
https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/devrtlkernel.html
2. The second method is by treating the FPGA as a blank slate and designing the system from scratch. This is the document that you are pointing to in the screenshot. The details are limited on this flow as it does involve an in-depth understanding of working with FPGAs. Because of the complexity of this type of design, you must first request access to the Alveo Vivado Lounge to get to that user guide:
https://www.xilinx.com/member/alveo-vivado.html
Regards,
~John
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