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Contributor
Contributor
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Registered: ‎05-04-2020

connection of DDR4_S_AXI_CTRL to XDMA on Alveo U200

I have a block diagram as follow for a design that is implemented on KCU1500:

Screenshot from 2020-05-26 13-14-44.png

I am trying to build the same design in a new project for Alveo U200. However when I add XDMA and DDR4 for U200 I see this:

Screenshot from 2020-05-26 13-11-38.png

As you see DDR4 has a new port C0_DDR4_S_AXI_CTRL. By looking at IP manual I can see that this is for ECC. But I don't know where I should connect it in my design. Is there any way to not use the ECC on this board and delete this port?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: connection of DDR4_S_AXI_CTRL to XDMA on Alveo U200

Hi @nzh 

You can possibly edit the DDR4 IP to remove ECC. 

What we normally do is add the AXI4 interface of the DDR4 to the mgmt PF of the PCIe/DMA, this would then give you an option to read from the ECC registers on a separate data path from your main data path. 

If you are using Vitis and a shell you won't have to make these connections yourself, the tools will put all this together for you. 

A good tool I like to use is I will build an example design from the Vitis library of example designs, then I will open up the block diagram and view the resulting BD. Here is a link to the Vitis examples, https://github.com/Xilinx/Vitis-Tutorials/tree/master/docs/vitis-getting-started

Regards,

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Contributor
Contributor
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Registered: ‎05-04-2020

Re: connection of DDR4_S_AXI_CTRL to XDMA on Alveo U200


@mcertosi wrote:

Hi @nzh 

You can possibly edit the DDR4 IP to remove ECC.  


@mcertosi How I can edit the DDR4 IP to not have DDR4_S_AXI_CTRL port when I use Alveo U200 board?

If you are using Vitis and a shell you won't have to make these connections yourself, the tools will put all this together for you. 


I am using the Vivado flow for this project. 


A good tool I like to use is I will build an example design from the Vitis library of example designs, then I will open up the block diagram and view the resulting BD. Here is a link to the Vitis examples, https://github.com/Xilinx/Vitis-Tutorials/tree/master/docs/vitis-getting-started

I used a couple of these examples in Vitis but when I open the Vivado project I don't see DRAM IP or DMA in the block diagram. I sent a picture of IP blocks that I see here:

https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/Can-I-have-access-to-PCIe-on-SDAccel-Vitis-OpenCL-solution/m-p/1111356#M1641

 

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