generate RTL kernel using U50

[sl82976818]

Hi,

I'm using Alveo U50 in vivado block design flow. When I press generate RTL kernel to generate the kernel and return to Vitis, I can see the part is xcu50-fsvh2104-2-e. 

"

Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xcu50-fsvh2104-2-e
INFO: [Device 21-403] Loading part xcu50-fsvh2104-2-e

"

But in Vitis setting, in the detail of the U50 platform, I can see the part name is "xcu50-fsvh2104-2L-e". They are different, There is a "L" extra.

So when I run the HW build, a Error will be occured.  The log below is in this file:"/Emulation-HW/binary_container_1.build/link/vivado/vpl/vivado.log'"

"

INFO: [OCL_UTIL] internal step: report locked IPs
INFO: [OCL_UTIL] internal step: source .local/dr.bd.tcl
ERROR: [BD 5-683] VLNV <mycompany.com:kernel:bd_fft:1.0> is not supported for the current part.
[OPTRACE]|1039|12|ipirun.tcl|sdx_vpl|1578587032800|END|Open bd and insert kernels|
ERROR: caught error: ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ip -vlnv mycompany.com:kernel:bd_fft:1.0 bd_fft_1"
invoked from within
"set bd_fft_1 [create_bd_cell -type ip -vlnv mycompany.com:kernel:bd_fft:1.0 bd_fft_1]"
(file ".local/dr.bd.tcl" line 27)
invoked from within
"source $dr_bd_tcl"
[17:23:52] Run vpl: Step create_bd: Failed

"

When I use U200 as the device, this will not happen. I have updated U50 platform in vitis and board list in vivado.

[mcertosi]

Hi @sl82976818 

The board files on our github board repo define the u50 as xcu50-fsvh2104-2L-e. 

Your Vivado project should point at these board files instead of what it is doing by default. 

Here is the board repo: https://github.com/Xilinx/XilinxBoardStore/tree/2019.1/boards/Xilinx/au50

You can use these TCL commands to set the current Vivado instance to the board repo you just downloaded 

set projName "your project name (in quotes)"
set projDir "./$projName"
set projPart "xcu50-fsvh2104-2L-e"
set projBoardPart "xilinx.com:au50:part0:1.0"
set_param board.RepoPaths /use_the_absolute_path/1.0
get_board_parts
create_project $projName $projDir -part $projPart
set_property board_part $projBoardPart [current_project]

The board file will have the correct value for projPart and projBoardPart

    <component name="part0" display_name="XCU50 FPGA" type="fpga" part_name="xcu50-fsvh2104-2L-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.xilinx.com/u50">

part_name = projPart

projBoardPart = vendor:name:(component)name:version (Values are found in board file)

[sl82976818]

Hi  mcertosi,

The above TCL commands will create a new project. I´m using a RTL kernel wizzard template so it can´t be a new project.

Is there some way to change board-part in the same project?

No matter I put the au50 board file into "vivado/data/boards" or using "set_param board.RepoPaths /use_the_absolute_path/1.0" I never can see the correct u50 downloaded fron github in the list of "setting/device/boards".

Thanks.

[mcertosi]

Hi @sl82976818 

Feel free to use any combination of the TCL commands. They do not need to be issued in sequence. 

Were you able to download the board files? 

I was under the impression that the RTL kernel wizard was board agnostic.. Can you send me some screenshots of what is preventing you from using set_property board_part $projBoardPart [current_project] to change the board in the RTL wizard flow? 

Regards,
M

[sl82976818]

I only used the menu/tools/Download lasted board and installed the .deb from U50 website. I don´t know which of them downloaded the wrong board part.

Finally I have solved the problem. I have downloaded the board file then redirected the setting/Board Repository to it. then choose again U50 board, it was fine.

Thank you.

[sl82976818]

Hi, 

We finally got a U50DD board. So this problem returned to the beginning:

In the boardstore, the au50/es/1.0 contains the u50dd archives, in au50/es/1.0/board.xml describes the board is u50dd, the part is part_name="xcu50-fsvh2104-2-e". 

But using "xcu50-fsvh2104-2-e" in vitis HW emulation build will cause a error. "ERROR: [BD 5-683] VLNV <mycompany.com:kernel:xxxxxxx:1.0> is not supported for the current part."

Is there some solution?

Do you want me open a new ticket for this topic?

Thank you.

[mcertosi]

Hi @sl82976818 

Why are you choosing the ES over the Production board files? 

https://github.com/Xilinx/XilinxBoardStore/blob/2019.1/boards/Xilinx/au50/production/1.0/board.xml 

The board.xml in the production board files point to "xcu50-fsvh2104-2L-e"

Would that work? 

Regards,

M

[sl82976818]

Hi mcertosi,

Because the ES marked U50dd which has part name xcu50-fsvh2104-2-e , and prodection marked U50 which has part name xcu50-fsvh2104-2L-e.

So, in vivado board flow U50dd can be connected to 2 SFP port.  U50 only one QSFP port.

But with U50dd can´t be used in vitis after compiled into ".xo". Maybe because the "xilinx_u50_xdma_201920_1" shell is only used for u50, "xcu50-fsvh2104-2L-e".   

I have tried to modify the part name to "xcu50-fsvh2104-2L-e" for U50dd in board.xml and all others files, then used "set_property board_part" to point to this repository. Nothing changed...

So how can u50dd be used as an acceleration card in vitis?

[mcertosi · Accepted solution]

Hi @sl82976818 

https://github.com/Xilinx/XilinxBoardStore/blob/2019.2/boards/Xilinx/au50/production/1.0/board.xml

the 2019.2 branch uses xcu50-fsvh2104-2-e for both u50DD and u50 production. 

Xilinx made a mistake in both the Master and 2019.1 branch. 

The u50 and u50DD are bistream compatible. 

Could you try this repository? 

Regards,

M

[sl82976818]

Hi mcertosi,

YES, this is right.

I used 2019.2 replaced the board downloaded automatically,  It works now.

Thank you!

[cmorsing]

Hi everyone,

I dont see the u50 in the board store anymore.

All the links above to github takes you to "page not found".

Anybody know how I can get the u50 board part in my setup?

[cmorsing]

Looks like the U50 board/part is back in Vivado 2020.1.1.

Might just be missing in vivado 2020.1

[emeryw]

Hi @cmorsing ,

Good to hear you are able to find the board in 2020.1.1. You can also acquire the board files from the Vivado Lounge: https://www.xilinx.com/member/alveo-vivado.html

You'll need to fill out the survey and request access, once granted, you'll have access to the board files and constraint XDC.

Best,

-Emery

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