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Contributor
Contributor
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Registered: ‎01-08-2020

no targets found issue during vitis embedded flow.

 

Hi,

 

I have generated a bit file for my custom SOC design Alveo U250 card. Im trying to execute hello world program using vitis embedded flow . Im getting no targets found ,im unable to debug this issue , can someone please help me out

 

ERE.png

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @mdpuma 

I think you are trying to connect to the MicroBlaze you have instantiated in your Alveo U250 custom RTL kernel. Could you confirm that is what you are trying to do or provide more clarity on the issue? 

Regards,

M

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Contributor
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Registered: ‎01-08-2020

Hi @mcertosi 

 

Yeah , I created a custom SOC design , where my custom IP is connected to microblaze. Earlier we used to follow Xilinx SDK embedded flow for testing our soc design on fpga.  But now Xilinx vitis itself provided embedded flow, there is no need of SDK seperately.  

I created an SOC in vivado 2019.2 version and generated a bit file .  Created an hardware definition file ( .XSA file) and exported it.

Created a platform project where i used my .XSA file and set board support packages there with microblaze as processor.

Created an application project and chosed  hello world template which Im trying to run on my hardware using .elf file .

This is the flow i have done till now but im unable to test my bit file on hardware.  No targets found issue is being faced . please help me out..

Thanks and regards

Prashanth

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @mdpuma,

I think you are mixing two flows. The Alveo acceleration flow wouldn't require you to create an XSA because the XSA is already created for you in the form of a platform or shell. 

If you download and install a shell, then use the RTL kernel flow to generate RTL that contains a MicroBlaze, you can program that onto your card. 

Here's a getting started guide for creating an RTL kernel https://github.com/Xilinx/Vitis-Tutorials/tree/master/docs/getting-started-rtl-kernels 

I think chapter 4 of this user guide goes over debugging with Vitis and .elf programming. You could use this to program your microblaze once it is on your card

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1165-zynq-embedded-design-tutorial.pdf

What board support package did you use? 

Regards,

M

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Contributor
Contributor
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Registered: ‎01-08-2020

Hi @mcertosi 

I'm using microblaze bsp .

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @mdpuma,

I still feel like you are mixing flows here. I looked, and I do not see a MicroBlaze BSP for Alveo. From what I can tell, you do not have a MicroBlaze on your card, so there is no way to run the program yet. 

Your notes say Alveo U250. So first thing you need to do is put a MicroBlaze on the Alveo U250. Do this by using the RTL kernel flow and creating an RTL kernel that has a MicroBlaze in it. 

The simplest flow is to compile that elf into the RTL kernel. Yes, you'll have to build your kernel each time you want to switch the elf with this approach. 

Second approach is to use XSCT. You need to have the microblaze already loaded onto the FPGA and a jtag cable connected to the maintenance port then you can open up a hardware server (vivado tool) and use xsct (vitis tool). 

Third approach is similar to the second, but you could use the virtual pcie jtag (xvc_pcie) instead of a physical jtag cable. 

Here is sample code and output for XSCT once you have a MicroBlaze on your acceleration card, you would use the xsct% dow command. You can use this XSCT documentation - https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk464819247.html?hl=xsct

xsct% connect
tcfchan#1
xsct% ta
  1  xcvu9p
xsct% targets -set -nocase -filter {name =~ "xcvu9p"}
xsct% ta
  1* xcvu9p   
xsct% ta
  1* xcvu9p
     2  MicroBlaze Debug Module at USER2
        3  MicroBlaze #0 (Running)
        4  MicroBlaze #1 (Running)
     5  Legacy Debug Hub
xsct% targets -set -nocase -filter {name =~ "MicroBlaze*#0"}
xsct% ta
  1  xcvu9p
     2  MicroBlaze Debug Module at USER2
        3* MicroBlaze #0 (Running)
        4  MicroBlaze #1 (Running)
     5  Legacy Debug Hub
xsct% dow <your_elf.elf>

Regards,

M

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Contributor
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Registered: ‎01-08-2020

Hi @mcertosi 

 

Thanks a lot for your clear explanation. I'm going through it. I will get back to you once I recheck the procedure. 

 

Thanks and regards

Prashanth.

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Contributor
Contributor
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Registered: ‎01-08-2020

Hi @mcertosi 

I have gone through the flow which I followed earlier.

.1. I did create an application project in vitis and through RTL kernel wizard option , it invoked to  vivado 2019.2  , in RTL kernel wizard I configured  number of master interface, kernel arguments and pointers, lite interface , block design or RTL design, no. Of clocks and resets. I chosed block design and it generated an SOC with microblaze as soft processor. I added my custom IP, UART, timer, axi interconnect block to it and generated RTL kernel i.e .XO file and has been exported to vitis. 

In vivado I exported the hardware and created a .xsa file , In vitis I created a platform project and chosed my custom platform i.e .xsa , with standalone bsp  and microblaze as processor ( I have attached jpg file plz go through it once )

I created an application project and selected hello world template to test my hardware on microblaze.

I have attached a few screenshots please go through it once. This is the flow I followed.

 

Thanks and regards

Prashanth

blockdesign.PNG
bsp.PNG
design info.PNG
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @mdpuma 

Are you still seeing problems? 

I see you haven't indicated you've generated an xclbin yet, so there still won't be a MicroBlaze on the board without that. 

Let me know what you need me to look at specifically. 

Regards,

M

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Contributor
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Registered: ‎01-08-2020

Hi @mcertosi 

Yes , problem has not been resolved yet. I tried to program my FPGA using JTAG cable . 

Sorry for not mentioning that I have generated .xclbin .  After programming the FPGA with bit file using jtga cable , I'm trying to test my hardware on microblaze using hello world program template by running the program.  Error is shown while launching the program. I have attached the screenshots of them. Please go through it.

 

Thanks and regards

Prashanth

err.PNG
fpga program.PNG
bit.PNG
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @mdpuma 

Not bad! Looking at the error message it looks like the tools see a MicroBlaze as a viable target. Look at 5,6, and 7 of the error. 

I'm not sure what you are showing me the second picture. I do not believe you should be programming a partial.bit nor a .xo file directly. 

It also looks like xsct is programming something, I'm not sure what is going on there just yet. 

Instead of running xsct in a script, can your run it line by line? It should work more in an interactive mode, then show me the entire interaction. I think you might be targeting something incorrectly, however I'm still happy with the progress we are making. 

There is no BSCAN USER2.1 but it looks like there is a USER1.1

Regards,

M

 

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Contributor
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Registered: ‎01-08-2020

 

Hi @mcertosi 

When we are programming using JTAG cable it is asking for .bit file extension.   So that's why I'm programming .bit file. ....xclbin has also been generated after building  target hardware in vitis. 

 

2. I actually didn't get your point , you have asked me to run  line by line I dint understand that , could you please brief me a bit more about it.?

 

3. In SOC , i have gone through  microblaze debug module IP , there in advanced section 

The JTAG user defined register used : user2 is selected , but In error it says no bscan user2.1. 

 

Thanks and regards

Prashanth.

 

 

15858499553886038008020401492495.jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @mdpuma 

In the picture attached it looks like xsct has found a microblaze debug module

 

You should be using xsct to try and connect to the module it has found. 

What happens when you connect to that debug module?

Regards,

M

 
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