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estebanpw
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Registered: ‎11-03-2020

resetn_0 port error: Unconstrained logical port

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Hello, 

I am new to FPGAs. So far I am following this tutorial to try to run some custom logic (an adder in the tutorial) on the FPGA.

However, when I try to generate the bitstream I get the "unconstrained logical port" error. I have seen several threads which indicate that to fix this there are two options available, namely (1) ignoring it via tcl command and (2) setting the appropriate pin in the constraints file. Since I am new to fpgas, I am kind of afraid to just ignore it, so I was trying to set the pin.

However, I am unable to find anywhere how to do pin planning on the alveo u200 accelerator card. 

The port that yields the error is the "resetn_0" which is automatically created when I run block automation. 

How can I properly configure the pin planning for this particular port on this board?

Thank you for your time!

 

For the record, the error is:

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: resetn_0.

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dsakjl
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Registered: ‎07-20-2018

Hi @estebanpw ,

from the Alveo U200 xdc file it seems that the correct pin for resetn_0 is AL20 which is identified as CPU_RESET_FPGA.

From the official xdc file:

# CPU_RESET_FPGA Connects to SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller
# Designed to be a active low reset input to the FPGA.
# set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS12 } [get_ports CPU_RESET_FPGA ];

So you should change this to:

set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS12 } [get_ports resetn_0 ];

 

If you want an automatic reset for your design on every machine reboot, probably you should connect resetn_0 to the PCIE reset_n port.

For the Alveo U200 you should add the following constraint:

set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS12 } [get_ports resetn_0 ];

The original constraint is from file "alveo-u200-xdc.xdc" contained in "xtp572-alveo-u200-xdc.zip", accessible as documented in UG1289.

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dsakjl
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Registered: ‎07-20-2018

Hi @estebanpw ,

which design port is connected to that pin?

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estebanpw
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Registered: ‎11-03-2020

Hello @dsakjl 

Thanks for your quick reply.

The port resetn_0 is connected to the "ext_reset_in" port in the Processory System Reset block. Both the block and the connection were generated by block automation. I am also attaching a screenshot (the orange wire corresponds to resetn_0)

 

estebanpw_0-1604476911663.png

Thank you for your time!

Esteban

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dsakjl
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Registered: ‎07-20-2018

Hi @estebanpw ,

from the Alveo U200 xdc file it seems that the correct pin for resetn_0 is AL20 which is identified as CPU_RESET_FPGA.

From the official xdc file:

# CPU_RESET_FPGA Connects to SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller
# Designed to be a active low reset input to the FPGA.
# set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS12 } [get_ports CPU_RESET_FPGA ];

So you should change this to:

set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS12 } [get_ports resetn_0 ];

 

If you want an automatic reset for your design on every machine reboot, probably you should connect resetn_0 to the PCIE reset_n port.

For the Alveo U200 you should add the following constraint:

set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS12 } [get_ports resetn_0 ];

The original constraint is from file "alveo-u200-xdc.xdc" contained in "xtp572-alveo-u200-xdc.zip", accessible as documented in UG1289.

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estebanpw
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Registered: ‎11-03-2020

Hello @dsakjl 

adding the second constraint:

set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS12 } [get_ports resetn_0 ];

 fixed it. Thank you a lot! Also, I did not know where I could find the official xdc file, so thanks for that too

Best regards,

Esteban

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