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Teacher muzaffer
Teacher
182 Views
Registered: ‎03-31-2012

simple custom u250 development questions

1) which clock is guaranteed to be running on a u250 board which is plugged into a pc but no xilinx run-time sw is installed or run. I assume pcie refclock should be up but what about sysclkX inputs?

 

2) what is the state of the CPU_RESET_FPGA (AL20) pin? I don't have the schematics so it's not clear if I can use this as an external reset.

 

Thanks.

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Xilinx Employee
Xilinx Employee
101 Views
Registered: ‎10-19-2015

Re: simple custom u250 development questions

Hi @muzaffer 

You should use the user clocks from the DDR. Try to avoid sharing the DDR system clocks with your logic. PCIe refclock is not usually the clock we recommend designing with since it can disappear during normal PCIe operation or switch speeds in the event of downtraining. 

I don't think you need to drive CPU_RESET_FPGA. By default it will be pulled up if unused. 

Regards,

M

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Teacher muzaffer
Teacher
92 Views
Registered: ‎03-31-2012

Re: simple custom u250 development questions

what about the SYS_CLKx differential inputs?

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Xilinx Employee
Xilinx Employee
88 Views
Registered: ‎10-19-2015

Re: simple custom u250 development questions

Hi @muzaffer 

Sys_Clk inputs are usually for the DDR Inputs, The recommended flow is to use IPI where these questions are handled for you with the board file. 

Otherwise I'd generate a design using Vitis, then open the resulting Vivado project and gather your constraints from there. 

Regards,

M

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