07-31-2007 02:45 AM - last edited on 04-13-2017 01:39 PM by stacias
Xilinx Community Forums - User Guidelines
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08-15-2012 05:58 AM
I want to ask some questions about xapp879 s6 pll reconfiguration,when I see the output clock of the reference design by chipcsope, I think the output clocks is wrong? But in the xapp879 s6 pll reconfiguration file, the author says that the refrence design is verification in hardware. thank!