I need the help of this forum once again, in other to successfully complete a design project.
I created a small verilog program (memory_usb) that communicates with the MIG core (by initialzing the memory inputs and outputs to logic 1) created in the rdf0126_ddr2_mem_tutorial that's provided by xilinx. whenever I synthesize this program, it gives the following error:
PortI of input buffer mig_inst/mig/memc3_infrastrsucture_inst/diff_input_clk.u_ibufg_sys_clk is connected to ground
-The verilog file memory_usb is within the folder 'mig_sp601'
-open the project mig_sp601 and add memory_usb.v as a sorce file
please at this point, I will appreciate all the help I can get