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Visitor
Visitor
7,173 Views
Registered: ‎10-14-2007

CORE Generator target device compatibility

Hi,

This should be an easy question:  I'd like to generate some IP modules that I can use with the Spartan-3A starter board; however I've noticed that lot of IPs don't explicitly support the Spartan-3A, while they do support the Spartan-3 (, for example the binary counter).  Can I generate the IPs for the 3 and use them on the 3A?

Thanks.
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Xilinx Employee
Xilinx Employee
7,158 Views
Registered: ‎08-13-2007

Re: CORE Generator target device compatibility

James,
 
Generally speaking, that should work. You will likely find it easier to invoke CORE Generator stand-alone and generate the core based on a supported family (e.g. Spartan-3) then use the files in your design, versus creating a new source (e.g. add xco) in ProjectNavigator (where you likely won't see it if the family isn't listed as supported). There are some minor differences between Spartan-3 and Spartan-3A, but as long as the core isn't directly impacted by these differences, you should be fine.
 
However, I would not recommend CoreGen for something like a binary counter. These simple cores (counters, muxes, etc.) are a carry-over from the days when the synthesis tools didn't do as good of a job as they do now. I recommend CoreGen for more complex cores (communication, DSP, etc.). For a simple binary counter, you should likely refer to the language templates in Project Navigator (Edit -> Language Templates -> VHDL [or Verilog as appropriate] -> Synthesis Contraints -> Counters.
 
I hope this helps.
 
 
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Visitor
Visitor
7,155 Views
Registered: ‎10-14-2007

Re: CORE Generator target device compatibility

That answers my question perfectly.  Thanks again.
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Xilinx Employee
Xilinx Employee
7,153 Views
Registered: ‎08-13-2007

Re: CORE Generator target device compatibility

James,
 
Glad to help.
I have done this retargeting for several cores that weren't officially supported in Coregen in my desired target family.
You do have to be aware of any underlying resource issues (difference in multipliers/DSP blocks, clocking resources, BlockRAMs, etc.) that could come into play.  This would not be a good approach for something with MGTs (serial multi-gigabit transceivers) as an example.
 
But for something like a counter, I think you are better off in HDL.
 
Good luck.
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