06-05-2008 08:29 AM
I'm using an existing design and flow which has already produced good, working images for a Virtex-4. However, I had to regenerate some memories to a smaller configuration, then I re-ran the build flow. Although it compiles OK (Synplicity) I get the following Error from ngdbuild for each RAM instance:
ERROR:NgdBuild:604 - logical block
'u_core/ARFI/ARF/BU2' with type
'dpram_256x36_blk_mem_gen_v2_1_xst_1' could not be resolved. A pin name
misspelling can cause this, a missing edif or ngc file, or the misspelling of
a type name. Symbol 'dpram_256x36_blk_mem_gen_v2_1_xst_1' is not supported in
ISE/ngdbuild Version : Release 9.1.03i ngdbuild J.33
I regenerated the memory (Simple Dual Port RAM) using coregen GUI (Release 9.1.03i, coregen J.30). It seemed to properly generate all the necessary files (*.v and *.ngc, specifically) in a coregen work area (./rtl/memory/coregen) . I copied these to the same directory as my other coregen generated files (./rtl/memory). With the RTL updated to instantiate the new dpram (4 isntances), I re-run the SynplifyPro (Version 7.7.1 - Build 028R) syntheis step successfully and generate a top level *.edf. So far, so good and the results are quite comparable to previous flows with the old dprams and the RAM instances look correct in the edif.
Now I invoke ngdbuild (Release 9.1.03i ngdbuild J.33) from the command line on a 64 bit linux machine. My invocation looks like this:
Everything is chugging along happily, and seems to find the newly generated dpram just fine, as well as an older and unchaged dpreg memory block:
Reading module "chip_fpga.ngo" ( "chip_fpga.ngo" unchanged since last run)...
Reading NGO file
Loading design module "../../rtl/memory/dpram_256x36.ngc"...
Loading design module "../../rtl/memory/dpreg_64x36.ngc"...
All seems good, until the "Checking expanded design ..." phase, where I get the above noted error for each of my four instances. Ngdbuild rolls over after these errors, and the flow is halted.
One other interesting note is that I get an identical error in coregen if I run IP->View Resource Utilization (Under Original Project Settings). Though it runs OK for the previously generated RAMs. Seems that perhaps something is missing in my setup or environment early in the coregen phase that carries through to the ngdbuild phase.
I googled and searched on Xilinx help database quite a bit, and although I see many a reference to "ERROR:NgdBuild:604", none of the recommended solutions seems to help, or doesn't seem to match my build flow options.
Many thanks for any suggestions!!!
07-16-2008 03:26 PM
04-23-2009 02:40 AM
I have the same issue.
I understand what causes the error, but I have no solution.
Here is my post:
I have a problem during 'translate' step of the following design:
I use Synplicity Synplify Pro 9.6.2 for synthesis and Xilinx ISE 10.1.03[K39] (service pack 3) for place and route.
2/° Design hierarchy:
Here is my design hierarchy:
TI_INTERFACE (entity : work.TI_INTERFACE)
The following modules are described in VHDL and synthetised into different libraries :
PLB_IPIF_BRIDGE is an instance of the module PLB2IPIC.
Synplify synthetizes all the submodules and the top-level module TI_INTERFACE except module PLB2IPIC which netlist is already available.
I grepped for patterns '(library ' and '(cell ' into the EDIF:
We can see that each instance of the design produces a cell into the EDIF file.
statements, but I have no issue with this).
We can see into the EDIF file that the module PLB2IPIC has been handled as a black-box and has produced a cell called 'plb2ipic_work_ti_interface_rtl_0'
I get the following error:
ERROR:NgdBuild:604 - logical block 'plb_interface/plb_ipic_bridge' with type 'plb2ipic_work_ti_interface_rtl_0' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name.
Symbol 'plb2ipic_work_ti_interface_rtl_0' is not supported in target 'virtex4'.
and implementations goes on.
Could somebody provide a solution for that?
Thanks a lot.
12-17-2009 08:59 AM
I changed my machine so I reinstalled my tools and now I am getting this error again...
Still ISE 10.1.03 (nt) K.39 and Synplify Pro 9.4
So is there a way to tell Synplify to look for the original balck-box name ?