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Newbie ddougher
Newbie
13,035 Views
Registered: ‎06-05-2008

ERROR:NgdBuild:604 when creating new memory

Hi -

 

I'm using an existing design and flow which has already produced good, working images for a Virtex-4.  However, I had to regenerate some memories to a smaller configuration, then I re-ran the build flow.  Although it compiles OK (Synplicity) I get the following Error from ngdbuild for each RAM instance:

 

>> 

ERROR:NgdBuild:604 - logical block
   'u_core/ARFI/ARF/BU2' with type
   'dpram_256x36_blk_mem_gen_v2_1_xst_1' could not be resolved. A pin name
   misspelling can cause this, a missing edif or ngc file, or the misspelling of
   a type name. Symbol 'dpram_256x36_blk_mem_gen_v2_1_xst_1' is not supported in
   target 'virtex4'.

<<

 

ISE/ngdbuild Version : Release 9.1.03i ngdbuild J.33

 


I regenerated the memory (Simple Dual Port RAM) using coregen GUI (Release 9.1.03i, coregen J.30).  It seemed to properly generate all the necessary files (*.v and *.ngc, specifically) in a coregen work area (./rtl/memory/coregen) .  I copied these to the same directory as my other coregen generated files (./rtl/memory).  With the RTL updated to instantiate the new dpram (4 isntances), I re-run the SynplifyPro (Version  7.7.1 - Build 028R) syntheis step successfully and generate a top level *.edf.  So far, so good and the results are quite comparable to previous flows with the old dprams and the RAM instances look correct in the edif. 

 

Now I invoke ngdbuild (Release 9.1.03i ngdbuild J.33) from the command line on a 64 bit linux machine.  My invocation looks like this:

 

ngdbuild

   -p XC4VLX100-12-FF1513

   -a

   -uc chip.ucf

   -dd .

   -sd ../../rtl/memory

   -sd ../../rtl/memory/coregen

   -sd ../../rtl/block
   ../../CR.00.00/synplify/chip_fpga.edf

   chip_fpga.ngd

 

 

Everything is chugging along happily, and seems to find the newly generated dpram just fine, as well as an older and unchaged dpreg memory block:

 

>>

Reading module "chip_fpga.ngo" ( "chip_fpga.ngo" unchanged since last run)...
Reading NGO file
/home/chippath/fpga/CR.00.00/xilinx/chip_fpga.ngo" ...
Loading design module "../../rtl/memory/dpram_256x36.ngc"...
Loading design module "../../rtl/memory/dpreg_64x36.ngc"...

<<

 

All seems good, until the "Checking expanded design ..." phase, where I get the above noted error for each of my four instances.  Ngdbuild rolls over after these errors, and the flow is halted.

 

One other interesting note is that I get an identical error in coregen if I run IP->View Resource Utilization (Under Original Project Settings).  Though it runs OK for the previously generated RAMs.  Seems that perhaps something is missing in my setup or environment early in the coregen phase that carries through to the ngdbuild phase.

 

I googled and searched on Xilinx help database quite a bit, and although I see many a reference to "ERROR:NgdBuild:604", none of the recommended solutions seems to help, or doesn't seem to match my build flow options.

 

Many thanks for any suggestions!!!

 

Regards,

 

Dave

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5 Replies
Xilinx Employee
Xilinx Employee
12,381 Views
Registered: ‎12-10-2007

Re: ERROR:NgdBuild:604 when creating new memory

Dave-

 

I am seeing this same problem!    Did you get a resolutions for this?

 

If so, can you please email me directly at craig.stiegman@xilinx.com?

 

Thanks!

Craig

 

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Highlighted
10,125 Views
Registered: ‎04-23-2009

Re: ERROR:NgdBuild:604 when creating new memory

Hi

 

I have the same issue.

 

I understand what causes the error, but I have no solution.

 

Here is my post:

 

 

 

I have a problem during 'translate' step of the following design:

 

1/° Tools:

 

     I use Synplicity Synplify Pro 9.6.2 for synthesis and Xilinx ISE 10.1.03[K39] (service pack 3) for place and route.
     Synplify is integrated into ISE.

 

 

 

2/° Design hierarchy:

 

     Here is my design hierarchy:

 

          TI_INTERFACE (entity : work.TI_INTERFACE)
            |
            +---- RST_GENERATION (entity : lib_ti_interface.RST_GENERATION)
            |
            +---- ROUTEUR_INTERFACE (entity : lib_ti_interface.IF_BUS_ROUTEUR)
            |       |
            |       +---- I_GESTION_MEM (entity : ip_routeur_tools.GESTION_MEM)
            |       |
            |       +---- I_MEMOIRE_8PORTS (entity : ip_routeur_tools.MEMOIRE_8PORTS)
            |               |
            |               +---- GEN_PORT_1.INST_MEMOIRE_PORT1 (entity : ip_routeur_tools.MEMOIRE_PORT)
            |               |       |
            |               |       +---- INST_MEMOIRE_PORT1 (entity : xilinx.DP_BRAM_XY)
            |               |
            |               +---- GEN_PORT_2.INST_MEMOIRE_PORT1 (entity : ip_routeur_tools.MEMOIRE_PORT)
            |               |       |
            |               |       +---- INST_MEMOIRE_PORT1 (entity : xilinx.DP_BRAM_XY)
            |               |
            |               +---- GEN_PORT_3.INST_MEMOIRE_PORT1 (entity : ip_routeur_tools.MEMOIRE_PORT)
            |                       |
            |                       +---- INST_MEMOIRE_PORT1 (entity : xilinx.DP_BRAM_XY)
            |
            +---- IP_UDP_RECEIVE (entity : lib_ti_interface.IP_UDP_RECEIVE)
            |       |
            |       +---- MSG_BUFFER (entity : lib_common.RAM_SYNC)
            |
            +---- TI_CONTROL (entity : lib_ti_interface.TI_CONTROL)
            |
            +---- TI_CONTROL_RESYNC (entity : lib_ti_interface.TI_CONTROL_RESYNC)
            |
            +---- VIDEO_TRANSMIT_BUFFER (entity : lib_ti_interface.VIDEO_TRANSMIT_BUFFER)
            |       |
            |       +---- MSG_BUFFER (entity : lib_common.RAM_ASYNC)
            |
            +---- VIDEO_TRANSMIT (entity : lib_ti_interface.VIDEO_TRANSMIT)
            |
            +---- VIDEO_RECEIVE (entity : lib_ti_interface.VIDEO_RECEIVE)
            |
            +---- VIDEO_RECEIVE_BUFFER (entity : lib_ti_interface.MBDA_FIFO_WRAPPER)
            |       |
            |       +---- CORE (entity : lib_ti_interface.FIFO_ASYNC)
            |               |
            |               +---- I_RAM (entity : lib_common.RAM_ASYNC)
            |
            +---- IP_UDP_TRANSMIT (entity : lib_ti_interface.IP_UDP_TRANSMIT)
            |       |
            |       +---- CHECKSUM_CALCULATOR (entity : lib_ti_interface.CHECKSUM_CALCULATOR)
            |
            +---- PLB_INTERFACE (entity : lib_ti_interface.PLB_INTERFACE)
                    |
                    +---- IPIF_CONTROLLER (entity : lib_ti_interface.IPIF_CONTROLLER)
                    |
                    +---- IPIF_RESYNC (entity : lib_ti_interface.IPIF_RESYNC)
                    |
                    +---- PLB_IPIF_BRIDGE (entity : PLB2IPIC)

      
      
      
3/° VHDL Modules:

 

     The following modules are described in VHDL and synthetised into different libraries :
      
          xilinx.DP_BRAM_XY

 

          ip_routeur_tools.GESTION_MEM
          ip_routeur_tools.MEMOIRE_8PORTS
          ip_routeur_tools.MEMOIRE_PORT

 

          lib_common.RAM_ASYNC
          lib_common.RAM_SYNC

 

          lib_ti_interface.CHECKSUM_CALCULATOR
          lib_ti_interface.FIFO_ASYNC
          lib_ti_interface.IPIF_CONTROLLER
          lib_ti_interface.IPIF_RESYNC
          lib_ti_interface.IP_UDP_RECEIVE
          lib_ti_interface.IP_UDP_TRANSMIT
          lib_ti_interface.MBDA_FIFO_WRAPPER
          lib_ti_interface.PLB_INTERFACE
          lib_ti_interface.IF_BUS_ROUTEUR
          lib_ti_interface.RST_GENERATION
          lib_ti_interface.TI_CONTROL
          lib_ti_interface.TI_CONTROL_RESYNC
          lib_ti_interface.VIDEO_RECEIVE
          lib_ti_interface.VIDEO_TRANSMIT
          lib_ti_interface.VIDEO_TRANSMIT_BUFFER

 

          work.TI_INTERFACE
      
  
      
4/° 'PLB_IPIF_BRIDGE' module:

 

     PLB_IPIF_BRIDGE is an instance of the module PLB2IPIC.
     This module is provided by a netlist (NGC file).
     In order for implementation to work, we specify the directory in which the NGC file is located in translate options so that Ngdbuild.exe find the netlist.

 

 

 

5/° Synthesis:

 

     Synplify synthetizes all the submodules and the top-level module TI_INTERFACE except module PLB2IPIC which netlist is already available.
     PLB2IPIC is considered as a black-box.
     Result is ti_interface.edn, a netlist in EDIF format.
     Hierarchy is kept.
  

 


6/° ti_interface.edn extract:

 

     I grepped for patterns '(library ' and '(cell ' into the EDIF:
 
     ~/synthesis> grep -e '(library ' -e '(cell ' ti_interface.edn
       (library VIRTEX
         (cell RAMB16 (cellType GENERIC)
         (cell SRL16 (cellType GENERIC)
         (cell IBUF (cellType GENERIC)
         (cell OBUF (cellType GENERIC)
         (cell LUT4_L (cellType GENERIC)
         (cell LUT4 (cellType GENERIC)
         (cell LUT3_L (cellType GENERIC)
         (cell LUT3 (cellType GENERIC)
         (cell LUT2_L (cellType GENERIC)
         (cell LUT2 (cellType GENERIC)
         (cell LUT1_L (cellType GENERIC)
         (cell LUT1 (cellType GENERIC)
         (cell MULT_AND (cellType GENERIC)
         (cell XORCY (cellType GENERIC)
         (cell MUXCY_L (cellType GENERIC)
         (cell MUXCY (cellType GENERIC)
         (cell MUXF6 (cellType GENERIC)
         (cell MUXF5 (cellType GENERIC)
         (cell BUFGP (cellType GENERIC)
         (cell BUFG (cellType GENERIC)
       (library UNILIB
         (cell FD (cellType GENERIC)
         (cell FDP (cellType GENERIC)
         (cell FDC_1 (cellType GENERIC)
         (cell FDC (cellType GENERIC)
         (cell FDPE (cellType GENERIC)
         (cell FDCE (cellType GENERIC)
         (cell INV (cellType GENERIC)
         (cell GND (cellType GENERIC)
         (cell VCC (cellType GENERIC)
       (library lib_common
         (cell ram_asyncZ1 (cellType GENERIC)
         (cell ram_asyncZ0 (cellType GENERIC)
         (cell ram_sync (cellType GENERIC)
       (library xilinx
         (cell dp_bram_xy_2 (cellType GENERIC)
         (cell dp_bram_xy_1 (cellType GENERIC)
         (cell dp_bram_xy (cellType GENERIC)
       (library ip_routeur_tools
         (cell (rename memoire_port_i_memoire_8ports_gen_port_1_inst_memoire_port1_2 "memoire_port_i_memoire_8ports_gen_port_1.inst_memoire_port1_2") (cellType GENERIC)
         (cell (rename memoire_port_i_memoire_8ports_gen_port_1_inst_memoire_port1_1 "memoire_port_i_memoire_8ports_gen_port_1.inst_memoire_port1_1") (cellType GENERIC)
         (cell (rename memoire_port_i_memoire_8ports_gen_port_1_inst_memoire_port1 "memoire_port_i_memoire_8ports_gen_port_1.inst_memoire_port1") (cellType GENERIC)
         (cell gestion_mem (cellType GENERIC)
         (cell memoire_8ports (cellType GENERIC)
       (library lib_ti_interface
         (cell ipif_controller (cellType GENERIC)
         (cell ipif_resync (cellType GENERIC)
         (cell plb2ipic_work_ti_interface_rtl_0 (cellType GENERIC)
         (cell checksum_calculator (cellType GENERIC)
         (cell fifo_async (cellType GENERIC)
         (cell plb_interface (cellType GENERIC)
         (cell ip_udp_transmit (cellType GENERIC)
         (cell mbda_fifo_wrapper (cellType GENERIC)
         (cell video_receive (cellType GENERIC)
         (cell ti_control_resync (cellType GENERIC)
         (cell ti_control (cellType GENERIC)
         (cell video_transmit (cellType GENERIC)
         (cell video_transmit_buffer (cellType GENERIC)
         (cell ip_udp_receive (cellType GENERIC)
         (cell if_bus_routeur (cellType GENERIC)
         (cell rst_generation (cellType GENERIC)
       (library work
         (cell ti_interface (cellType GENERIC)

 

     We can see that each instance of the design produces a cell into the EDIF file.
     Cell name is based on entity name and not on instance name (except for memoire_port instances because there are some 'generate'

     statements, but I have no issue with this).
  

 


7/° My problem

 

     We can see into the EDIF file that the module PLB2IPIC has been handled as a black-box and has produced a cell called 'plb2ipic_work_ti_interface_rtl_0'
 
     Translation does not work because Ngdbuild.exe tries to find the netlist of a module called 'plb2ipic_work_ti_interface_rtl_0'.
     Our NGC file is the netlist of a module called 'plb2ipic'.

     I get the following error:

 

          ERROR:NgdBuild:604 - logical block 'plb_interface/plb_ipic_bridge' with type 'plb2ipic_work_ti_interface_rtl_0' could not be resolved.

                         A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name.

                         Symbol 'plb2ipic_work_ti_interface_rtl_0' is not supported in target 'virtex4'.


  
     So the problem is this black-box name 'plb2ipic_work_ti_interface_rtl_0' in the EDIF file generated by Synplify during synthesis.
 
     When I modify the EDIF file manually after synthesis and replace 'plb2ipic_work_ti_interface_rtl_0' by 'plb2ipic', then translation works fine,

     and implementations goes on.
  

 


Could somebody provide a solution for that?
 

Thanks a lot.

 

 

  
Julien

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10,115 Views
Registered: ‎04-23-2009

Re: ERROR:NgdBuild:604 when creating new memory

It turned out this specific problems only happens with Synplify 9.6.2

I returned to Synplify 9.4 and it works fine

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Visitor maxbuder
Visitor
9,778 Views
Registered: ‎06-16-2009

Re: ERROR:NgdBuild:604 when creating new memory

Unfortunatly this problems reoccurs in synplify version c-2009.6. Are there any know flags or the like for synplify?

 

 

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8,483 Views
Registered: ‎04-23-2009

Re: ERROR:NgdBuild:604 when creating new memory

OMG !

I changed my machine so I reinstalled my tools and now I am getting this error again...

Still ISE 10.1.03 (nt) K.39 and Synplify Pro 9.4

So is there a way to tell Synplify to look for the original balck-box name ?

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