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Adventurer
Adventurer
18,984 Views
Registered: ‎09-18-2007

FPGA Power On Reset!

I'm new to Xilinx FPGAs (I usually use Actels!)
 
I'm really confused about how to initilize the registers on power-up. I've been told not to use the GSR as it has lots of skew.
The link below is useful and what I use in Actel FPGAs. What I don't quite understand is that if I use a syncronous reset, then this is making nested IF statements one level deeper and result in slower clock speeds. Also, what signal do I use as the reset signal since Xilinx FPGAs are not live on power-up.
 
I here also that I can use the INIT statement to clear/set signals for synthesis

attribute INIT : string;

attribute INIT of DRS_S : signal is "00";

 
 but for simulation I also need to initialize the signal:

signal DRS_S : std_logic_vector(1 downto 0) := "00";

 

This is OK for logic with no feedback that needs to be reset. But how do I reset the logic with feedback?

 

I'm going round in circles so any comments are appreciated.

 

Thanks

 

 
 
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3 Replies
Highlighted
Instructor
Instructor
18,890 Views
Registered: ‎08-14-2007

Re: FPGA Power On Reset!

For SRAM-based FPGA's, power-on reset initiates the program load or configuration.  How this happens depends on the mode pins.  There are users guides for configuration for each FPGA family that describe the possible methods.

Initialization values from INIT statements are downloaded to the part in the bitstream.  Essentially in addition to configuring the LUT's and routing, the bitstream contains initial values for every flip-flop and RAM bit in the device.  Since this is a serial process, registers are initialized at different times throughout the configuration process, but since the logic is not active yet you can consider this happening before "global reset".

GSR is not an asynchronous reset/preset signal in the hardware.  Think of it as the signal that holds everything quiescent during configuration and for a programmable number of configuration clocks thereafter.  When GSR goes inactive, which happens exactly once after configuration, the whole FPGA is allowed to run as programmed.  This is the edge that can cause issues in any synchronous systems which require multiple flip-flops to start on the same clock edge.  The first issue stems from the configuration clock being asynchronous (in most cases) from the clock to the state logic.  The second issue is the large skew in the GSR net to various parts of the FPGA.

Typically state machines are designed with an asynchronous reset term.  It is a good practice to drive this reset with a signal that is synchronous to the clock of the state machine.  A simple method for a "power-on" reset with synchronous release is to instantiate a series of D flip-flops as a shift register.  For active high reset these would be FDP flip-flops, which are initialized to 1 on GSR or if their preset input is asserted.  The actual preset input can be tied low (inactive) if you don't need to re-assert reset.  The input to the shift register would be tied low, so after a few clocks the output will synchronously go low.  The point of using more than one flip-flop is to give enough time for all state machine flip-flops to be out of global set/reset.  I typically use three flip-flops for this.

Flip-flops in the Xilinx FPGA's all have a reset input that can be configured as synchronous or asynchronous.  It can also be configured to reset low or high (preset).  This is independent of the INIT value of the flip-flop, however if not otherwise specified, the INIT value will match the reset state.  In this default case you also don't need to do anything special for simulation, as long as you drive the asynchronous (or synchronous) reset input to you machine at the start of simulation.  GSR is driven for 100 nS by default in simulation for library elements.

HTH,
Gabor
-- Gabor
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Newbie manumathews
Newbie
18,654 Views
Registered: ‎04-24-2008

Re: FPGA Power On Reset!

Hi,
    I too am a beginner with Xilinx FPGAs. I want to know how we can use the GSR to reset the FPGA to known state. I have started with a small design which interfaces with the LCD on Spartan3E starter kit. The config file is in platform flash. The external async reset is mapped to a push button. But when the board is powered on, the LCD is displaying junk. Since I have a pulldown on ther LCD enable signal, I am sure that the LCD is getting driven from inside the FPGA logic. Once I push reset, everything is proper. I want to make sure that the end of the FPGA configuration process issues a reset to all my flops. How can I do this?
 
My code for flops look like this
always @ (posedge clk or posedge rst)
begin
   if (rst)
   begin
        ...........
   end
   else
   begin
      ...........
   end
end
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Instructor
Instructor
18,645 Views
Registered: ‎08-14-2007

Re: FPGA Power On Reset!

I'm not familiar with the LCD on that board, but it is possible that the FPGA finishes configuration before the LCD is ready to start up.  It is not hard to create a longer reset signal internal to the FPGA.  The typical reset from the Xilinx appnote uses 4 FDP flip-flops arranged as a shift register with the serial in and asynchronous preset both tied to zero.  The shift register thus starts up as all 1's and after GSR is released it shifts until the output finally goes low and stays low.  This is generally used as an internal reset signal synchronous to your system clock (on the release edge).

If you need a much longer reset, you can add a counter that is reset by the shift register, and use its high-order bit as an active low reset for the remainder of your logic.  Just make sure that the counter stops when its high order bit goes high, or you will continue to get reset signals.

HTH,
Gabor
-- Gabor
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