**UPGRADE YOUR BROWSER**

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser: Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

- Community Forums
- Xcell Daily Blog
- Technical Blog
- About Our Community
- Announcements
- Welcome & Join
- General Technical Discussion
- Programmable Devices
- UltraScale Architecture™
- 7 Series FPGAs
- Virtex® Family FPGAs
- Spartan® Family FPGAs
- Xilinx Boards and Kits
- Configuration
- Design Tools
- Installation and Licensing
- Synthesis
- Simulation and Verification
- Implementation
- Design Entry
- Timing Analysis
- Vivado TCL Community
- HLS
- Design Methodologies and Advanced Tools
- SDAccel
- Design Tools - Others
- Embedded Systems
- Embedded Development Tools
- Embedded Processor System Design
- Embedded Linux
- Zynq All Programmable SoC
- SDSoC Development Environment
- OpenAMP
- Intellectual Property
- PCI Express
- Networking and Connectivity
- MIG
- DSP and Video
- System Logic

turn on suggestions

Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

Showing results for

- Community Forums
- :
- Xilinx Products
- :
- Design Tools
- :
- Archived ISE issues (Archived)
- :
- Fixed point numbers in VHDL

Topic Options

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic to the Top
- Bookmark
- Subscribe
- Printer Friendly Page

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

06-23-2008 08:07 PM

Hi there, I am working with the floating point numbers for implementation of an IIR filter. Now, I need to represent the filter coefficients as fixed point numbers. These can be signed numbers with an integer part and an exponent part. I have got a vague idea that I need something like a SIGN bit, a certain number of INTEGER part bits , and fractional part. Now, I want to represent them as 16 bit fixed point nukmbers upon which, I can perform addition, subtraction, multiplication etc. But at the moment, I am stuck in chosing a data type for such numbers. Is it going to be a std_logic_vector as a port and then conversion to a signal with data type signed or something? and then back conversion but how to decide how many bits are integer part and how many are fractional part and how to find out if it's a 2's complement number or what? Any suggestions please? Thanks

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-10-2008 08:43 AM

Maybe you know this maybe you don't:

For signed numbers the number of bits QI needed to represent a floating point value is given by the following equation:

QI = 1+ ceiling(log2(max(abs[alpha_max,alpha_min]))) where alpha is the floating point value. For |6| this => QI = 1+ ceiling(2.58) = 1+3 = 4 integer bits needed.The resolution of the fixed point number is given by the equation:

Epsilon = 1/(2^QF) where QF is the number of fractional bits to the right of the decimal point. For 24.20 : epsilon = 9.5367 e^-7.

Range and resolution : -2^(QI-1) <= alpha < 2^(QI-1) – 2^(QF) where the word length WL = QI+QF and the sign bit is lumped with QI.

Matlab documentation at available at the mathworks.com website has a lot of good info on working with fixed point data.

Hope this helps,

CTW

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-10-2008 03:10 PM

Hey mate,

Thanks very much for your reply. At least someone replied to it.

Well, I have seen lots and lots of these theories but I want to implement it in VHDL. I am currently working with two's complement form by taking the sign bit, integer part and the fractional part as seperate numbers, hence performing the operations seperately on all of these parts but it looks a bit complex and lengthy line of code.

Another option, I am trying is by converting the coefficients decimal values to binary values with bicimal point e.g. 6.5 = 110.10000 and then taking this as a simple binary number without the bicimal point and converting it into a decimal integer only value, that I can convert to a signed binary number using built-in VHDL function like signed() or to_signed() which takes only integer arguments.

Any suggestions at all r welcome.

Thanks,

Kamran

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-10-2008 08:26 PM - edited 07-13-2008 06:00 PM

You need to convert your floating point coefficients to fixed point numbers first somewhere. If you do the conversion to signed 16-bit fixed point numbers in Matlab, they will in 2's complement format. When you use the signed 16-bit fixed coefficients in VHDL and use "signed" type for all operands, all arithemetic (add, subtract, multiply, etc) will be in 2's complement (works the same in simulators as well as synthesis tools) and you don't have to worry about it (i.e. no need to separate signed bit, integer part, fractional part.). Actually the beauty of fixed point numbers is that the decimal point (or bicimal point as you call it) is "imaginary" in the sense that you just need to keep track where it is in your mind and don't have to treat the integer part or fractional part any differently in your logic.

Cheers,

Jim

Message Edited by jimwu on 07-10-2008 11:28 PM

Message Edited by jimwu on 07-13-2008 09:00 PM

Cheers,

Jim

Jim

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-11-2008 05:51 PM - edited 07-11-2008 05:53 PM

Hi Jim,

- Thanks very much for your reply. But I forgot to mention that the platform I am using is ISE 6 and the target is Spartan-3. Are you still sure that It'll be possible to use floating-point numbers? I mean what data-type I need to use? I have tried using real but It doesnt work, it says vsim failed: annotated testbench or sth, and when I try to do conversion of these real numbers to signed binary numbers I mean by using the function to_signed () or signed(), it only accepts integer value so e.g. I want 1.094523 to be represented in signed binary format, this function won't accept it unless I use another function to convert it to an integer first which is of no use to me.
- By the way, what do you mean by FP over here? Is it Fixed-point or Floating-point? I guess Fixed-point.
- So, do I have to convert the decimal number by itself to a signed-binary number by myself? But there'll be an input value and I think the only data type accepted as a port is std_logic_vector for this purpose? (I beg your pardon if I am wrong).
- I have also seen some stuff about the Fixed-point packages whic has got the data-types like u-fixed and s-fixed with positive and negative index like s_fixed [3:-3]; which means there are 3 digits after the decimal/bicimal point. It sounds very nice and simple but I don't know how to use packages. Can I use these packages for my software? I mean ISE 6?
Thanks very much for your help,

Kamran

Message Edited by kamwad on 07-11-2008 05:53 PM

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-13-2008 06:26 PM

Please see may answers inline:

> 1. Thanks very much for your reply. But I forgot to mention that the platform I am using is ISE 6 and the target is Spartan-3. Are you still sure that It'll be possible to use floating-point numbers? I mean what data-type I need to use? I have tried using real but It doesnt work, it says vsim failed: annotated testbench or sth, and when I try to do conversion of these real numbers to signed binary numbers I mean by using the function to_signed () or signed(), it only accepts integer value so e.g. I want 1.094523 to be represented in signed binary format, this function won't accept it unless I use another function to convert it to an integer first which is of no use to me.

You can use "real" data type for simulation, but it won't work in synthesis (AFAIK, neither xst nor synplify support it). As I mentioned, you need to convert the floating point numbers to fixed point numbers first if you don't want to handle floating point math yourself. Since you're designing a filter, I assume you know Matlab, which you can use to easily convert floating point numbers to fixed point numbers (check Matlab fixed point tool box fi()).

> 2. By the way, what do you mean by FP over here? Is it Fixed-point or Floating-point? I guess Fixed-point.

Sorry about that. I changed FP to fixed point in my previous message to avoid confusion.

> 3. So, do I have to convert the decimal number by itself to a signed-binary number by myself? But there'll be an input value and I think the only data type accepted as a port is std_logic_vector for this purpose? (I beg your pardon if I am wrong).

Yes, if you only want to deal with fixed point numbers inside FPGA, you will have to do the conversion. You can use signed or unsigned data type for ports as well, which are closely related to std_logic_vector.

>4. I have also seen some stuff about the Fixed-point packages whic has got the data-types like u-fixed and s-fixed with positive and negative index like s_fixed [3:-3]; which means there are 3 digits after the decimal/bicimal point. It sounds very nice and simple but I don't know how to use packages. Can I use these packages for my software? I mean ISE 6?

You can use the fix point package like any other VHDL package. I think it is relatively new, so it may not be fully supported in synthesis tools. As for any DSP design, you need to simulate (again, I hope you use Matlab) your algorithm when moving from floating point to fixed point. If you have done that, you should already have the fixed point representations of your coefficients.

Cheers,

Jim

Cheers,

Jim

Jim

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-14-2008 06:32 PM

Hi Jim,

Thanks very much for your response and the clarfication of the FP and stuff.

- I do know about MATLAB and sorry, I forgot to mention that I've already implemented the filter in MATLAB (SIMULINK) and I was able to generate the HDL code from it as well but I am trying to implement it by myself in VHDL. I've tried the fi() and I could convert the filter coefficients to the 16-bit signed binary numbers. Is there a way that I could link these values of coefficients generated from MATLAB to be used in VHDL (I mean if I store them in a file?) And if it's possible, then will it be possible to use them straight from that file into the FPGA ROM (I mean if I store the coefficients in the ROM)?
- Does this kind of code look suitable for Spartan-3 ? I mean from the resources point-of-view?
- I'll have to truncate the product to make it 16-bit, what is the best criteria for that?
- One more question about the Fixed-point packages, I don't actually know how to use the VHDL packages. I mean is it like creating a new project with one .vhd package file and then the testbench(es) as I've seen on the VHDL.org website, there are 4 or 5 files in it. I don't know how to compile them? Where to copy them first? Or do I need to include them in the same project where I want to use them (I mean the IIR filter project)

Thanks very much Jim. I really appreciate it. I am sorry if I am being a pain.

Cheers,

Kamran

- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content

07-15-2008 07:39 PM

1. check http://toolbox.xilinx.com/docsan/xilinx9/help/iseg

2. It depends what you are doing. You may also want to take a look at Spartan-3A.

3. Simulation.

4. Well, get a good VHDL reference book.

Cheers,

Jim

Cheers,

Jim

Jim