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sbroderick
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Registered: ‎06-26-2008

ISE 10.1 synthesizing the wrong source?

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I am presently developing for the Spartan 3. My top level source is a schematic and I have VHDL modules both hand written and generated/linked to StateCAD designs below that. When I synthesize though, it synthesize ONLY a source generated by StateCAD (the most recently changed one at that). There are 6 other sources on the same level of the tree with it that should be synthesized, but the summary only lists that one.

 

Has anyone seen this? It seems like it is just ignoring my changes, as well. Closing and restarting doesn't phase it. I also made sure to do Rerun All on the synthesis process.

 

I am certain my schematic is selected.

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sbroderick
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Registered: ‎06-26-2008
It turns out that there is a bug with 10.1. By making a new project and top-level source the problem is fixed. Xilinx is attempting to fix it.

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sbroderick
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Registered: ‎06-26-2008
It turns out that there is a bug with 10.1. By making a new project and top-level source the problem is fixed. Xilinx is attempting to fix it.

View solution in original post

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