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Participant
Participant
6,899 Views
Registered: ‎08-31-2007

ISE 9.2.03 - Strange behavior when architecture name in VHDL file changed

When I'm working on a project and editing source files in ISE 9.2.03, I've noticed if I change the name of the architecture in my VHDL modules, the source file will cease to appear in the Sources window.  I have to go and remove the file from the project using the Libraries tab, then re-add the file for it to show up.  Am I the only one that sees this behavior / is there a reason for this behavior?  I don't remember this happening before in earlier versions that I have used.
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Adventurer
Adventurer
6,889 Views
Registered: ‎08-01-2007

I just tried what you described using one of the example designs (stopwatch) ... changing the architecture name from "inside" to "outside", and did not see any problems in ISE (Sources pane shows "stopwatch - outside (stopwatch.vhd)" as expected).

Are you using 9.2.3? Can you reproduce what you describe using the stopwatch example?


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Xilinx Employee
Xilinx Employee
6,878 Views
Registered: ‎09-14-2007

Hi,

This sounds like a bug in the autoparser of ISE. There must be something in your design files that is causing the autoparser to fail. When you change the architecture name, Proj Nav will try to reparse the file and if it sees any sort of errors in the parsing stage, it will remove the file and not add it to the hierarchy.

Please open a tech support case and submit the files so it can be further investigated

Thanks
Duth

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