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jianlong
Observer
Observer
17,730 Views
Registered: ‎10-26-2008

Let's talk about the skill about shorten the run time of ISE.

Let's talk about the skill about shorten the run time of ISE.

We know the run time is unavoidable longer than before in those large device such as V5SX or V5LXT, so we must use the new feature about the ISE tools.

 

By now, I know below skills can improve your productivity:

 

1) use the latest tools, ISE 10.1 is faster than ISE9.2, install the latest sw package.

 

2) use the partion or smartguide feature in the ISE, unfortunately we always forget it.

 

3) set the strategy as "short runtime" before you have to tune up the design performance at last.

 

But I what to know whether there is any skills about shorten the run time.

 

For example, my design has 5 channels of 72-taps filters in SX95T(used partion feature), I rewirte some source code in the other module, such as :

-----------------------------------------------------

old version:

     output1<= data[1]&& data[2];

 

changed to:

 

new version:

     output1<= data[3]&& data[4];

-----------------------------------------------------

then we have to wait for a long long time, while we expected  it should be short, because the whole project is changed only a little. And this scene is very common in our debug period?

 

So could you share your skills with such case?
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12 Replies
morphiend
Explorer
Explorer
17,701 Views
Registered: ‎08-14-2007

Well from you stated, the thing that will help your run-time with that type of change is using partition-based design. By isolating the area that you're changing you can minimize the time necessary to rebuild that portion.

 

One SIMPLE way of partitioning your design is building it in pieces. This requires setting up your project properly, but can be very helpful. By this, I mean lets say your design consisted of this:

 

Top   -- ModuleB

  |

  ModuleA

         /     \

        /       \

ModuleC     ModuleD

 

In this design, ModuleA uses ModuleC and ModuleD. And the top-level build uses Module A and ModuleB. These individual modules can synthesized individually and brought into their respective parent projects, by including the NGC files from the previous build. This allows you to only rebuild the individual pieces as necessary. Now, take care w/ timing on these individual pieces. If the NGC files are not available at each build step timing analysis could lead to false assumptions of max operating speed. There are other things to worry about, too, but's usually one of the biggest culprits.

 

Another way of speeding up the design is floorplanning. The less choices the Mapper/Placer has the faster it will run. Just to give an example, I had a complex system that would take 3+ hours to complete MAP and PAR. After performing some very 'simple' floorplanning, the design now completes those steps in 20-30 minutes. That's a time reduction of 6x!

liy
Xilinx Employee
Xilinx Employee
17,690 Views
Registered: ‎08-02-2007

I'm not saying a JOKE but how about trying  on a 64bit machine especially LINUX 64  with bigger memory

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jianlong
Observer
Observer
17,678 Views
Registered: ‎10-26-2008

I think it's the same under Linux, whenever 32 bit or 64 bit, but we could use multi-processor under LINUX, and we could use PLANAHEAD under Windows.

 

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czhe
Adventurer
Adventurer
17,663 Views
Registered: ‎09-10-2008

"2) use the partion or smartguide feature in the ISE, unfortunately we always forget it."

 

How do we use this in 10.1? I've found everything to be slower in 10.1 since I upgraded from 9.2.

 

Thanks. 

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jianlong
Observer
Observer
17,652 Views
Registered: ‎10-26-2008

我估计你应该认得中文的,就直接给你回啦,

 

是这样的,你可以选择顶层目录下面的你想要做PARTION的模块 ,点击鼠标右键,弹出菜单中有“New partition”,选中就可以了:)

 

If you can not read this, pls let me know.

 

 

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jianlong
Observer
Observer
17,647 Views
Registered: ‎10-26-2008

Hi, morphiend:

 

Thanks for your detail reply, and I did like you state before, I just want to know, do we have the tech to lock down

the  routed result in the iterative progressive design?

 

I found the "smartguide & partition" still re-map and re-par, why not use the previous result?

 

Thanks! :smileyhappy:

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czhe
Adventurer
Adventurer
17,635 Views
Registered: ‎09-10-2008

Hi jianlong,

 

Unfortunately I could not read it :(. Could you translate for me?

 

Thanks,

czhe 

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jianlong
Observer
Observer
17,622 Views
Registered: ‎10-26-2008

Ha~~Ha~~

 

Sorry for that!

 

It's very simple, u can follow this instruction:

 

1)Select "Source window"->Source tab;

 

2)Select the sub-module of your project;

 

3)Right-click, pop the menu, then select "new partition", then you'll make this module as a usable partition;

 

4)Repeat step3, you can got partions as your will.

 

Tips: after the ISE10.1  version, you can select multipul sub-module at the same time, then you can finish at one click;

 

Is that clear enough?

 

:)...

liy
Xilinx Employee
Xilinx Employee
17,552 Views
Registered: ‎08-02-2007

remap or re PAR will happen when any of the following  happens

 

 

1 code modification in this parition

2 constraints chang

3MAP PAR options change

 

 

 

see detailes in xapp918 

 

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liy
Xilinx Employee
Xilinx Employee
7,934 Views
Registered: ‎08-02-2007

try smartxplore if you are using Linux

 

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zklc123
Newbie
Newbie
6,216 Views
Registered: ‎08-16-2010

v6系列 可以用partion技术吗?我试了几次都不行。右击,partion选项是灰色的。

不知您是否在v6上用过partion技术?

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jianlong
Observer
Observer
6,089 Views
Registered: ‎10-26-2008

对于V6的设计而言,如果要缩短运行时间,鄙人愚见是:

 

(1)用最新版本的12.2编译器,但是要打上最新的V6的布线算法补丁;

 

(2)并打开MAP和PAR的多线程(mt)选项;

 

这两项带来的改进还是很明显。

 

除此之外,你还是可以尝试一下Smartguide增量编译选项,而Partion技术对于设计的要求具有硬copy的要求,所以适用范围很小,实际意义愚以为不大。

 

末了,再说点题外话,要想运行时间很少,可能最有效的办法是根据设计所需要的数据流来优化管脚分配方案,并按需求而不是过高要求地做好时序约束,前面的那些技巧可能都是“亡羊补牢”式的措施。

 

懒得写e文了,呵呵。

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