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Visitor kingmu
Visitor
4,835 Views
Registered: ‎05-27-2008

Not seeing expected simulation from counter

I am using ISE WebPACK 10.1. I am trying to code the 4-bit VHDL counter that is on page 55 of the XST User Guide. In the past, when I use the ISE Simulator, I have selected Combinatorial for Clock Information; I make the clock manually in the test bench waveform editing window. Then, in the editing window, I toggle the other various inputs to test my entity. I have simulated many examples and they always work as expected. In this case, I clock C, and keep CLR low. When I sim it, I expect to see Q count from 0000 up. Unfortunately all I see is 'X' for all levels. I don't understand why Q is not being set.

 

What am I doing wrong?

 

Thank you,

Sam 

 

 

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