Problems with instantiation with Verilog (using xapp458)
I have tried to implement xapp458 which is an application to use the DDR2 SDRAM in Spartan 3A. However, for this module, vlog_xst_bl4_main_0, it clearly instantiates the following module vlog_xst_bl4_top_0 top0 ( .auto_ref_req (auto_ref_req), .wait_200us (wait_200us), ... );
Yet as shown in the image I have attached, it doesn't allow me to add vlog_xst_bl4_top_0 module to it! I don't get it, it works for every other module instantiating other modules. Why?
I now start wondering if Xilinx had really tested these reference designs before release.
I had the same problem with XAPP458 ref design. I did the following to get rid of this issue:
commented out //`include "../source/sdramtst/vlog_xst_bl4_parameters_0.v" on each file and copied the contents of vlog_xst_bl4_parameters_0.v to the same place. So now the design passed synthesis. However, I still have problem with constraints in the provided ucf. An example:
ERROR:NgdBuild:753 - "C:/Xilinx_projects/sp3an458/source/framebuf.ucf" Line 773: Could not find instance(s) 'vlog_xst_bl4_inst/infrastructure_top0/cal_top0/cal_ctl0' in the design. To suppress this error specify the correct instance name or remove the constraint.