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Contributor
Contributor
7,625 Views
Registered: ‎04-09-2015

AXI Interconnect INTERCONNECT_CLK dependencies

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Hey everyone,

 

just a quick question (somehow I can't find it in the papers...)

 

Lets say I have 1 AXI Interconnect with one Master-Port connected to MIG and 2 Slave-Ports connected to modules (basically multiple slaves sharing the MIG).

If the modules run at 100MHz, does the AXI Interconnect have to run at 200 MHz? Or is it also possible to have Interconnect + modules running at the same clock?

I know this will limit throughput, just wondering about functionality here.

 

 

Little background:

I have the setup from above with an AXI Interconnect and modules running at 200MHz (round-robin arbitration). The first write from the 1st module goes through but every following write can't take place because the AXI Interconnect doesn't assert the READY-Signals anymore although the MIG has them asserted. Reading still goes through the AXI Interconnect.

 

Cheers,

Steffen

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Contributor
Contributor
14,170 Views
Registered: ‎04-09-2015

Re: AXI Interconnect INTERCONNECT_CLK dependencies

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AWREADY problem is solved, it was the BREADY signal.

AXI4_specification says "The default state of BREADY can be HIGH, but only if the master can always accept a write response in a single cycle." Later in the document it says "a write response must always follow the last write transfer in the write transaction of which it is a part".

 

Seems like the AXI Interconnect takes that into account, my bad.

 

Clock domain issue has been resolved with that, it seems to work.

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Contributor
Contributor
7,604 Views
Registered: ‎04-09-2015

Re: AXI Interconnect INTERCONNECT_CLK dependencies

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To make it more clear, I posted a screenshot of the chipscope waveform.

example.jpg
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Contributor
Contributor
14,171 Views
Registered: ‎04-09-2015

Re: AXI Interconnect INTERCONNECT_CLK dependencies

Jump to solution

AWREADY problem is solved, it was the BREADY signal.

AXI4_specification says "The default state of BREADY can be HIGH, but only if the master can always accept a write response in a single cycle." Later in the document it says "a write response must always follow the last write transfer in the write transaction of which it is a part".

 

Seems like the AXI Interconnect takes that into account, my bad.

 

Clock domain issue has been resolved with that, it seems to work.

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