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Participant jimfred
Participant
10,093 Views
Registered: ‎10-31-2011

AXI Uartlite, baud rates

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The AXI UartLite 2.0 dialog to Re-Customize lists specific baud rates in a pull-down with a maximum baud rate of 921600. Is there a suggested method of modify the baud rate generator to select other baud rates such as 250000 (for DMX512) or higher baud rates such as 2,000,000?

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Participant jimfred
Participant
16,150 Views
Registered: ‎10-31-2011

Re: AXI Uartlite, baud rates

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Steps to add 2.0Mbaud to UartLite IP Block without hacking files in the Xilinx directory...

  • Add UartLite blocks to block design as required. 
    Save and exit Vivado
  • Search for *axi_uartlite*.XML files under the .srcs directory.
    Expect names of the form...
    ./project.srcs/sources_1/bd/myBlockDesign/ip/myBlockDesign_axi_uartlite_0_0\myBlockDesign_axi_uartlite_0_0.xml
    Expect 1 file for each block plus, perhaps, another.
    These files appear to be project-local cached copies of IP.
  • Edit and save each file after making this modification:
    Search for text...
    <spirit:enumeration spirit:text="921600">921600</spirit:enumeration>
    ...and add...
    <spirit:enumeration spirit:text="2.0Mbaud">2000000</spirit:enumeration>
  • Open Vivado, Block Diagram. In gui, expect to see new baud option. Select as required and build.

Notes:

  • IP revision/upgrades my require that these steps be repeated.
  • Changes are local to this project. Original Xilinx IP files remain un-molested.
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4 Replies
Participant jimfred
Participant
10,091 Views
Registered: ‎10-31-2011

Re: AXI Uartlite, baud rates

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I found a post on the forums here that suggests editing an .mpd file which might be for an older .ISE system. For the UartLite, the newer equivalent might be something like C:\Xilinx\Vivado\2014.2\data\ip\xilinx\axi_uartlite_v3_0\component.xml. 

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Participant jimfred
Participant
10,089 Views
Registered: ‎10-31-2011

Re: AXI Uartlite, baud rates

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Modifying the axi_uartlite_v3_0\component.xml file worked!

I was able to get 2,000,000 baud using a 100MHz AXI clock.

 

Next, I really should figure out how to make a project-specific copy of the modified IP rather than hacking code in the \xilinx directory.

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Participant jimfred
Participant
16,151 Views
Registered: ‎10-31-2011

Re: AXI Uartlite, baud rates

Jump to solution

Steps to add 2.0Mbaud to UartLite IP Block without hacking files in the Xilinx directory...

  • Add UartLite blocks to block design as required. 
    Save and exit Vivado
  • Search for *axi_uartlite*.XML files under the .srcs directory.
    Expect names of the form...
    ./project.srcs/sources_1/bd/myBlockDesign/ip/myBlockDesign_axi_uartlite_0_0\myBlockDesign_axi_uartlite_0_0.xml
    Expect 1 file for each block plus, perhaps, another.
    These files appear to be project-local cached copies of IP.
  • Edit and save each file after making this modification:
    Search for text...
    <spirit:enumeration spirit:text="921600">921600</spirit:enumeration>
    ...and add...
    <spirit:enumeration spirit:text="2.0Mbaud">2000000</spirit:enumeration>
  • Open Vivado, Block Diagram. In gui, expect to see new baud option. Select as required and build.

Notes:

  • IP revision/upgrades my require that these steps be repeated.
  • Changes are local to this project. Original Xilinx IP files remain un-molested.
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Newbie kawinter
Newbie
8,184 Views
Registered: ‎06-18-2015

Re: AXI Uartlite, baud rates

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In case someone stumbles onto this and starts working with higher and higher baud rates, there are a few things I've discovered about this from various sources (and a few experiments) so I thought I'd mention them here...

 

1. The maximum bit rate is clock/16.

2. Do not make assumptions about the accuracy of the synthesized rate (at least without looking at the actual implementation of the UARTLite block). Grab an analyzer or scope and check.

3. The next step down from maximum bit rate appears to be clock/32. Anything in between these two points will snap up or down to a supported rate.

 

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