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Explorer
Explorer
15,379 Views
Registered: ‎12-06-2013

Block Memory Generator IP doesn't show AXI4 interface option

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I was trying to create an AXI4 slave BRAM in Vivado 2013.4 and there were no options available for this. The BMG was v8.1. User guide was available for v7.3 only.

bmg.png

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Xilinx Employee
Xilinx Employee
23,840 Views
Registered: ‎07-11-2011

Re: Block Memory Generator IP doesn't show AXI4 interface option

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Hi,

 

Hope you are using 2013.4 only, but I can see it at my end.

I guess you are trying this in IPI, not IP catalogue and hence unable to view it?

 

BRAM_AXI4.png

 

Also page -91 of PG058 says that in IPI BRAM has only two modes Native and BRAM controller, so guess GUI is in accordance with doc.

 

 

Regards,

Vanitha

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9 Replies
Xilinx Employee
Xilinx Employee
15,378 Views
Registered: ‎07-11-2011

Re: Block Memory Generator IP doesn't show AXI4 interface option

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Hi,

 

BMG 8.1 supports AXI4

http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_1/pg058-blk-mem-gen.pdf

 

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Explorer
Explorer
15,371 Views
Registered: ‎12-06-2013

Re: Block Memory Generator IP doesn't show AXI4 interface option

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vsrunga, 

 

Agreed, page 89 of the manual shows the BMG with the AXI S interface available. When I open the IP to customize it, however, I was unable to select AXI4 in BMG 8.1. 

 

I did find a work around with using the AXI BRAM controller 3.0 using Vivado which is fine for me, however, I want the XILINX folks to know that I was unable to use the BMG 8.1 in the way page 89 of the manual shows it. Here is the way I had to do it in Vivado:

alternate_axi4_bmg.png

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Xilinx Employee
Xilinx Employee
23,841 Views
Registered: ‎07-11-2011

Re: Block Memory Generator IP doesn't show AXI4 interface option

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Hi,

 

Hope you are using 2013.4 only, but I can see it at my end.

I guess you are trying this in IPI, not IP catalogue and hence unable to view it?

 

BRAM_AXI4.png

 

Also page -91 of PG058 says that in IPI BRAM has only two modes Native and BRAM controller, so guess GUI is in accordance with doc.

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Explorer
Explorer
15,361 Views
Registered: ‎12-06-2013

Re: Block Memory Generator IP doesn't show AXI4 interface option

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That is correct, I am using 2013.4 (Vivado) and the IP Integrator, which I have to admit I didn't realize there was a difference between core usage in the IPI vs. IP catalog which is a bit confusing. I was able to change the device to AXI4 S when using the IP Catalog but I will show you why this was confusing. Here are both windows showing the differences between the IP and IPI. Since this is resolved I will mark this answer as accepted  (FYI, thanks for your help on this! :)

bmg confusion.png

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Xilinx Employee
Xilinx Employee
15,347 Views
Registered: ‎08-01-2008

Re: Block Memory Generator IP doesn't show AXI4 interface option

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Block Memory Generator Core configuration in IP catalog and IP integrator not same. You need to use AXI BRAM controller with BMG core when using IP I flow. For detail refer PG058 Customizing the Core with IP Integrator section
Thanks and Regards
Balkrishan
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Explorer
Explorer
15,343 Views
Registered: ‎12-06-2013

Re: Block Memory Generator IP doesn't show AXI4 interface option

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Agreed, they are not the same which is very confusing. In a block design you can right click on the schematic and select "Add IP" which will give you a list of IP that different than from the IP catalog. I have my issue solved but I am trying to help out and mention that this is confusing. If it XILINX intended to have an IP catalog, IP that can be imported into a block design and an IP integrator I am only suggesting that it be clear...

 

I spent some extra time yesterday just trying to verify that these three things together where the root cause to my problem. I read the manual on the BRAM and just didn't understand the distinction between all of the IP options. 

 

Furthermore, the reason why I am having this issue is because I am trying to use Vivado like XPS (visually connecting IP blocks) for the AXI modules which doesn't work with this method but I will post that in a different issue :)

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Xilinx Employee
Xilinx Employee
15,100 Views
Registered: ‎08-01-2008

Re: Block Memory Generator IP doesn't show AXI4 interface option

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you can find better documentation with vivado 2014.1 release. Information is added for IPI flow. In future we also working on context based help which can serve your purpose better way.
Thanks and Regards
Balkrishan
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Visitor raghup17
Visitor
13,634 Views
Registered: ‎03-26-2014

Re: Block Memory Generator IP doesn't show AXI4 interface option

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Just stumbled on this post. As suggested, it seems like a BRAM can be given an AXI only by using the BRAM controller in the IP Integrator mode. However, even with the BRAM controller design, I am not able to increase the width of my BRAM. I am able to set the word width in the BRAM controller, and presumably this gets propagated to the BRAM block. This propagation step is failing during synthesis. I tried with Vivado 2013.3. I haven't tried 2014.1.

 

Does this mean that IPI mode not support BRAM blocks wider than 32 bits in BRAM controller mode? So if I want an AXI interface to a wide BRAM block (256 bit), do I have to take the non-IPI route to design my system?

 

 

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Visitor rwood
Visitor
7,163 Views
Registered: ‎11-12-2015

Re: Block Memory Generator IP doesn't show AXI4 interface option

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Im using vivado 2015.4 and attempting to use Block Memory Generator 8.3.  I had the same issue with the AXI4 option not showing up in the IP config menu and having to go to the IP Catalog to see this option.  Not sure why Xilinx has not fixed this obvious problem.

As for using the IP, in my dual port application I need the AXI interface on one port and use the second port with custom logic.  But either this can't be done or its not clear how to set it up.  As other readers have noted, if you select BRAM Controller mode, then all the port settings are grayed out and not selectable.  In AR60838 xilinx says:  

"When using the memory with an AXI BRAM Controller, the Mode option of the BMG GUI must be set to "BRAM Controller" to allow the AXI BRAM Controller to parameterize the core. For all other uses, select Stand Alone mode, and ensure that all settings are compatible."

But BRAM Controller mode will not allow you to specify port memory widths/depth.  So for me this IP appears to be worthless.  

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