05-12-2017 08:11 AM
I would like a way to check the amount of data in an AXI-Stream FIFO from PL. Without seeing any flags I can pull out from block customization my initial instinct would be to sniff the handshaking going on between it and the downstream block. The only problem is as long as the valid and ready flags remain asserted there doesn't seem to be a way to check how much data is actually being transferred... The downstream block is xilinx ip as well so I don't have any way to add a register simply to keep count of data out.
End goal is send an interrupt when the fifo hits some threshold value. Any ideas?
05-12-2017 11:15 AM
When you customize the FIFO in the IP catalog, the Config tab allows you to set up programmable full and empty thresholds. There's also a checkbox for a FIFO occupancy count. Those can be routed to the PL.
05-12-2017 01:23 PM
05-15-2017 09:05 AM
05-15-2017 09:06 AM
Of course if I did this then the FIFO would need to AXI lines -- one for me to check status on and a final one to pull the data out back to the ARM Cores. I know there must be a more reasonable way -- I'm completely over thinking this.
05-15-2017 12:30 PM
The AXI-Lite interface is typically used as a simple way to read and write control registers within an IP. It performs the same function as the IPIF in ISE's EDK. If I understand what you're want, you'd design it with 2 registers: one that allows the PS to read the occupancy count and the TREADY bit, and one that read and shifts out the FIFO. Remember that the occupancy count can also be routed to the PL by making the signal external.
05-16-2017 01:46 PM
I don't think I made my problem clear enough, we seem to be circling it :)
From the PS I would like to be able to pull data out from the FIFO (AXI4-Lite); which is trivial to implement. In addition to that the data being pushed into the FIFO needs to come from an AXI-Stream interface. The tricky part is I only want to read from the FIFO after some expected amount has been dumped into it. Three ways to monitor this are via polling (which I don't want to do), using the Receive Fifo Programable Full Threshold value but this number is subject to constant change so cannot be set statically in the IP, or generating an interrupt when it hits this value by calculating it externally and monitoring the occupancy of the FIFO. The only appropriate way to do this for my application is via the interrupt.
My options using Xilinx IP are : AXI-Stream FIFO, AXI4-Stream Data FIFO, and FIFO Generator.
AXI-Stream FIFO : offers AXI4-Lite PS interface however does NOT have an option to read the occupancy count.
AXI4_Stream Data FIFO : doesn't offer using AXI4-Lite but DOES have the occupancy count
FIFO Generator : Identical to AXI4-Stream Data FIFO wrt the parameters needed (no axi4-lite -> axi-stream but does have occupancy)
So essentially my two options are implement an AXI4-Lite <--> AXI-Stream interface or somehow monitor the number of transactions that are entering the stream fifo in order to determine occupancy. The problem is i'm not sure if the latter is even achievable since if both up and downstream modules are fully pipelined the TVALID and TREADY flags will remain asserted after each transaction masking the number of transactions actually occurring...
My ideal situation would be if the AXI-Stream FIFO offered a PL routed occupancy register but they don't which is making this a nightmare.
Thanks for the help !
05-17-2017 05:19 AM
Yes, it looks like there isn't quite the combination of interfaces to drop into your design neatly. I took a glance at the AXI-Stream FIFO, and while it does have an AXI_Lite interface on one side, the other side isn't just an AXI Stream; it looks like it's made to attach to another IP, probably the Ethernet IP that is referenced in the product guide.
Maybe look at an AXI Memory Mapped to Stream Mapper and an AXI protocol converter (or two)?