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Participant anupkini
Participant
556 Views
Registered: ‎05-16-2012

FIFO Gen 13.2, bready never goes high

HI All,

 

I am trying to simulate AXI Async FIFO using  FIFO Gen 13.2 in Vivado 2018.1 and QuestaSim 10.7

 

The axi_m_bready signal, generated from the fifo, never goes high, even after reset. The same design worked fine in Vivado 2017.4.1. After upgrade of iPs the design fails on write response transaction because of bready never going high.

 

Simulation SetUp

Vivado 2018.1

QuestaSim 10.7

FIFO Generator 13.2

 

Kindly let me know if this is a know issues or any suggestions on debugging this further.

 

Thanks,

Anup.

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1 Reply
Xilinx Employee
Xilinx Employee
523 Views
Registered: ‎07-23-2012

Re: FIFO Gen 13.2, bready never goes high

Can you please share .xci file to reproduce and investigate this issue at my end?
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