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Visitor 11223344
Visitor
728 Views
Registered: ‎04-17-2018

FIFO rd/wr_rst_busy max time

FIFO generator spec PG057 does not seem to specify a max time for rd_rst_busy and wr_rst_busy after rst input is released.

In my case, I do need to specify it as the FIFO write is controlled by an external processor which has no knowledge of the FIFO status.

Is there a max specified anywhere for the 7-series family FIFO IP?

If not, can I safely use what I am getting out of the simulation model?

Thanks.

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3 Replies
Moderator
Moderator
703 Views
Registered: ‎08-08-2017

Re: FIFO rd/wr_rst_busy max time

Hi @11223344

The wr_rst_busy and rd_rst_busy signals are available only for UltraScale device built-in FIFOs, and Common Clock Block RAM/Distributed RAM/Shift Register FIFOs with synchronous reset. I wonder you are getting this for 7 series FIFO. Please check on device.

The FIFO can be accessed when these signals are de-asserted. if the motioning of these signals is not possible, the best way is to perform the Structural Simulation (Post Synthesis/Post Implementation) to get assertion time for these signals . ( The  max time for rd_rst_busy and wr_rst_busy is not specified because, it is depends on the clock ratio.

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Visitor 11223344
Visitor
666 Views
Registered: ‎04-17-2018

Re: FIFO rd/wr_rst_busy max time

Hello pthakare,

Thanks for the feedback.

The FIFO IP (Native, Independent Clocks Block RAM, First Word Fall Through) was generated with Vivado2016.4 (FIFO Generator 13.1) for an Artix-7 part and does indeed have 2 busy outputs.

Please see extract from …sim_netlist.v below:

       // Tool Version: Vivado v.2016.4 (lin64) Build 1756540 …

       // Device      : xc7a …

       (* CHECK_LICENSE_TYPE = "fifo_16_16_1k,fifo_generator_v13_1_3,{}" *) ... (* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)

       ...

       module fifo_16_16_1k

          (rst,

           wr_clk,

           rd_clk,

           din,

           wr_en,

           rd_en,

           dout,

           full,

           empty,

           prog_full,

           wr_rst_busy,

           rd_rst_busy);

I would like to avoid running post implementation simulation as they take forever.

What accuracy will I get by running a simulation with the fifo..._sim_netlist.v/vhdl model?

Thanks

 

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Moderator
Moderator
654 Views
Registered: ‎08-08-2017

Re: FIFO rd/wr_rst_busy max time

Hi @11223344

The behavioral simulation models provide a simplified model of the core while the structural simulation models (UniSim) are an accurate modeling of the internal structure of the core. In very few cases we have seen unexpected result with Behavioral Simulation so its better to perform Structural simulation for sanity check.

You may want to create a test design containing only FIFO to lessen the Post implementation Simulation time. 

The FIFO IP (Native, Independent Clocks Block RAM, First Word Fall Through) was generated with Vivado2016.4 (FIFO Generator 13.1) for an Artix-7 part and does indeed have 2 busy outputs.

I will also perform the Structural Simulation at my end and let u know the rst_busy deassertion timings.

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Reply if you have any queries, Give Kudos and accept as Solution

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Reply if you have any queries, give kudos and accept as solution
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