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FIFO read back value are not macth with the write value in same address

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Contributor
Posts: 35
Registered: ‎09-08-2016
Accepted Solution

FIFO read back value are not macth with the write value in same address

Hi Expert,

 

    I'm using bram IP(8.3) for a project.I have found that the address 0 value which I write to bram through portA is not equal the address 0 value which read back form portB, but equal to address 1.For all the value of portA are equal to the address plus 1 of portB.

    For an example: Firstly write value to BRAM from Port A: addr0(0x03020100)  addr1(0x07060504) addr2(0x0b0a0908)........

Capture.PNG

    Secondly ,read the value from BRAM through portB. The value I expect is:addr0(0x03020100)  addr1(0x07060504) addr2(0x0b0a0908)........    .But actually it is :addr0(0x00000000)  addr1(0x03020100) addr2(0x07060504)........

Capture1.PNG

 

The following is ths BRAM setting:

Capture2.PNG

Capture3.PNG

Capture4.PNG

Capture5.PNG

Capture6.PNG

 


Accepted Solutions
Contributor
Posts: 35
Registered: ‎09-08-2016

回复: FIFO read back value are not macth with the write value in same address

Hi Gabor,

   I have found the reason: When writing to the block RAM, two clock cycles are required(actually I just give 1 cycle enable when writing),because the design is accessing a block RAM, requiring an address in one cycle and data read in the next.But still thanks for your help!

 

Best Regards!

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All Replies
Contributor
Posts: 35
Registered: ‎09-08-2016

回复: FIFO read back value are not macth with the write value in same address

Hi Expert,

    I have done another experiment: change the start address of portB when reading. I have found that the first value read back from portB is always 0. the value of  the following address is match.

Highlighted
Instructor
Posts: 9,048
Registered: ‎08-14-2007

回复: FIFO read back value are not macth with the write value in same address

In the port B register settings you have checked "Primitives Output Register".  This creates an additional delay when reading.  So the issue is not that you're getting data from the wrong address, but that your data is delayed until the next read enable.  If you need the data immediately following the first read enable, you need to uncheck that box.

-- Gabor
Contributor
Posts: 35
Registered: ‎09-08-2016

回复: FIFO read back value are not macth with the write value in same address

Hi Gabor,

   I have found the reason: When writing to the block RAM, two clock cycles are required(actually I just give 1 cycle enable when writing),because the design is accessing a block RAM, requiring an address in one cycle and data read in the next.But still thanks for your help!

 

Best Regards!