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Contributor
Contributor
3,173 Views
Registered: ‎05-15-2014

Latency Error in FIFO generator IP

hello

 

I am using Vivado 2016.4 and FIFO Generator 13.1.

 

When I try to generate FIFOs using the options

  • independent write-read clocks for Block RAMs
  • enabled standard FIFO
  • enabled output registers using
  • enabled "Embedded Reg AND Fabric Reg"

the IP graphical user interface reflects a read latency of 2 clock cycles.

 

Actually since 2 levels of more pipeline stages are added in this case the total read latency becomes 3 clock cycles.

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5 Replies
Scholar dpaul24
Scholar
3,166 Views
Registered: ‎08-07-2014

Re: Latency Error in FIFO generator IP

It is because you have enabled 'Output Registers'.

 

Uncheck the box beside 'Output Registers', keeping only 'Embedded Registers' visible from the drop-down. Your Read Latency value will then decrease.

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FPGA enthusiast!
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Contributor
Contributor
3,149 Views
Registered: ‎05-15-2014

Re: Latency Error in FIFO generator IP

I think you do not understand the problem.

 

If we use built in FIFO we have 1 clock cycle latency.

If we use built in FIFO with enabled output registers and enabled "Embedded Reg" we have 2 clock cycles latency.

If we use built in FIFO with enabled output registers and enabled "Fabric Reg" we have 2 clock cycles latency.

If we use built in FIFO with enabled output registers and enabled "Embedded Reg AND Fabric Reg" we have 3 clock cycles latency.

 

However the graphical user interface of IP generator shows 2 clock cycles latency for the latter case.

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Scholar dpaul24
Scholar
3,137 Views
Registered: ‎08-07-2014

Re: Latency Error in FIFO generator IP

Now your explanation is clear and I also see it in one of my FIFOs.

 

Have you chosen a Block RAM based FIFO?

 

As I have never used a combination of both of them, so on checking the documentation, FIFO Generator v13.1 PG057 April 5, 2017, Pg# 118, I see that....

For standard BRAM FIFOs, a latency of two cycles is added to the output when both registers are chosen as shown in Figure 3-21

 

The safest way would be to run a simulation of both type of FIFOs and see the latency at the output.

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FPGA enthusiast!
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Contributor
Contributor
3,130 Views
Registered: ‎05-15-2014

Re: Latency Error in FIFO generator IP

Yes. As I wrote in my first message I used Black RAM FIFOs for transferring data from one clock domain to the other.

The problem in the user intarface must be fixed. Actually, I do not know the situation in the newest version.

 

I checked the latency of 3 clock cycles in hardware without problem.

 

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Xilinx Employee
Xilinx Employee
3,061 Views
Registered: ‎09-20-2012

Re: Latency Error in FIFO generator IP

Hi @fatih.aydogdu

 

This is IP GUI display issue, I have filed CR 982775 to get this corrected.

Thanks,
Deepika.
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