08-16-2017 04:42 AM
I am using Vivado 2016.4 and FIFO Generator 13.1.
When I try to generate FIFOs using the options
the IP graphical user interface reflects a read latency of 2 clock cycles.
Actually since 2 levels of more pipeline stages are added in this case the total read latency becomes 3 clock cycles.
08-16-2017 05:11 AM
It is because you have enabled 'Output Registers'.
Uncheck the box beside 'Output Registers', keeping only 'Embedded Registers' visible from the drop-down. Your Read Latency value will then decrease.
08-16-2017 05:26 AM
I think you do not understand the problem.
If we use built in FIFO we have 1 clock cycle latency.
If we use built in FIFO with enabled output registers and enabled "Embedded Reg" we have 2 clock cycles latency.
If we use built in FIFO with enabled output registers and enabled "Fabric Reg" we have 2 clock cycles latency.
If we use built in FIFO with enabled output registers and enabled "Embedded Reg AND Fabric Reg" we have 3 clock cycles latency.
However the graphical user interface of IP generator shows 2 clock cycles latency for the latter case.
08-16-2017 05:52 AM - edited 08-16-2017 06:04 AM
Now your explanation is clear and I also see it in one of my FIFOs.
Have you chosen a Block RAM based FIFO?
As I have never used a combination of both of them, so on checking the documentation, FIFO Generator v13.1 PG057 April 5, 2017, Pg# 118, I see that....
For standard BRAM FIFOs, a latency of two cycles is added to the output when both registers are chosen as shown in Figure 3-21
The safest way would be to run a simulation of both type of FIFOs and see the latency at the output.
08-16-2017 06:15 AM - edited 08-16-2017 07:06 AM
Yes. As I wrote in my first message I used Black RAM FIFOs for transferring data from one clock domain to the other.
The problem in the user intarface must be fixed. Actually, I do not know the situation in the newest version.
I checked the latency of 3 clock cycles in hardware without problem.
08-17-2017 04:35 AM
This is IP GUI display issue, I have filed CR 982775 to get this corrected.