06-12-2018 09:29 AM
I am trying to get a SDP BRAM to simulate correctly in Vivado 2017.3. My aim is to write 1,2,3,4,.. to a BRAM of depth 16. Once the address reaches 1111, I want to start reading the BRAM and expect its output to go 1,2,3,4,... The issue is that the output is stuck at 0 and I dont know if there is an issue in the way I am setting read/write enable signals or something else.
Below is the way I have instantiated the BRAM and the simulations show all important signals. Currently I have connected wea and enb to high. Port A is always enabled. Memory_output is stuck at 0. Can someone please help me with this?
blk_mem_gen_0 U (
.clka(CLK), // input wire clka
.wea(high), // input wire [0 : 0] wea
.addra(addr), // input wire [3 : 0] addra
.dina(data_in), // input wire [15 : 0] dina
.clkb(CLK), // input wire clkb
.enb(high), // input wire enb
.addrb(addr), // input wire [3 : 0] addrb
.doutb(memory_out) // output wire [15 : 0] doutb
06-13-2018 12:49 PM
Your write enable (WEA) should only be high when you are trying to write to the RAM. I'm assuming this is when your data input is changing. You leave WEA high when you are trying to read the RAM, meaning you are writing and reading from the same cell. Depending on how the RAM is configured, you are getting collisions and thus bad data.
06-20-2018 04:47 AM