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Explorer
Explorer
601 Views
Registered: ‎08-31-2017

RAM_PERFORMANCE parameter in xilinx SDP RTL template

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Hi, 

 

 In Tools-->Language Templates, it has RTL template for xilinx  simple Dual Port Single Clock RAM with Byte-Write. It has one parameter RAM_PERFORMANCE which can be either HIGH_PERFORMANCE or LOW_LATENCY. However, I don't find where it defines among doc or forum. Thus, I need your help to guide what they are.

 

All the best,

Nan-Sheng

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Moderator
Moderator
972 Views
Registered: ‎11-09-2015

Re: RAM_PERFORMANCE parameter in xilinx SDP RTL template

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Hi @nanson,

 

This parameter is just for to configure if you are using a register at the output of the memory. If yes, you add one clock of latency but you can go at higher frequency.

 

Check UG473, optional output Registers:

memory.PNG

 

Hope that helps,

 

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
568 Views
Registered: ‎08-31-2017

Re: RAM_PERFORMANCE parameter in xilinx SDP RTL template

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 Does anyone ever use the RTL template of BRAM inference provided by Vivado ? How do you configure the parameter ? Thanks

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Moderator
Moderator
973 Views
Registered: ‎11-09-2015

Re: RAM_PERFORMANCE parameter in xilinx SDP RTL template

Jump to solution

Hi @nanson,

 

This parameter is just for to configure if you are using a register at the output of the memory. If yes, you add one clock of latency but you can go at higher frequency.

 

Check UG473, optional output Registers:

memory.PNG

 

Hope that helps,

 

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos