09-07-2017 07:47 AM
Does anyone have any source code (VHDL preferred, Verilog also OK) for very short AXI stream FIFO, with independent master/slave clocks ? Thanks.
The FIFO Generator 13.1 has minimum FIFO depth 16. (why is this? isn't it a very normal case when using FIFO just to cross clock domain we want it to be as short as possible? the other common use case for very short FIFOs is breaking up long TREADY routing paths?)
I have lots of AXIS FIFOs in my design to help route AXIS streams between various IP, and I want to reduce the overall logic utilisation of all these FIFOs
This picture shows exactly what I need, except that I would like depth <16 (eg 2, 4, 8 is OK)
Since the ratio of master/slave (or slave/master) clock frequencies in my case is never more than 2:1 different, I don't see why I need to store >=16 values in the FIFO.
Maybe its simple I'm just not quite sure how to code it myself - maybe some tricky details like the cross-clock sync logic or constraints - thanks !
09-07-2017 08:00 AM
Check if AXI4-Stream Clock Converter is what you need (page 11)
11-10-2017 01:09 PM
I do not want to sprinkle salt into the soup (german saying), but I made the observation that the axi4stream infrastructure contain also an (undocumented) amount of intenal buffers.
I was also falling into this trap some months ago.
Take a look into this aspect if you use the axi4stream infrastructure.
If you made the same experience, I´ll be happy if you´ll inform me about the amount of bytes you have in the interconnect in your configuration.