05-17-2018 06:51 AM
I am learning FPGA design using Verilog and I am having issues using the Block Memory Generator. I am using a Basys 3 dev board with an artix-7. I feel I am making a mistake in my code, but can't find it. The Generator is customized to be single port with 8 bit width of read and write, and 256 word depth. It is also set to write first. Thanks for you help.
module mem_top( input clk, input [4:0] BTN, output [15:0] LED ); reg mem_clk = 1'b0; reg [7:0] addr = 8'd60; reg [7:0] din = 8'd45; reg [7:0] ledoutput = 8'b0; wire [7:0] dout; reg en = 1'b1; reg wen = 1'b0; reg hasWritten = 1'b0; reg hasChanged = 1'b0; reg isPressed = 1'b0; reg testled = 1'b0; assign LED[7:0] = ledoutput[7:0]; assign LED[14:8] = 8'b0; assign LED = testled; blk_mem_gen_0 mem( .clka(mem_clk), .dina(din), .douta(dout), .addra(addr), .ena(en), .wea(wen) ); always@(*) begin if(hasChanged == 1'b0) begin ledoutput <= dout; hasChanged = 1'b1; end end always@(*) begin isPressed = BTN; end always@(*) begin if(isPressed) begin if(hasWritten == 1'b0) begin testled = 1'b1; wen = 1'b1; mem_clk = 1'b1; mem_clk = 1'b0; wen = 1'b0; hasWritten = 1'b1; end end end endmodule
05-20-2018 11:41 PM
What is the anomalous behavior with this code ? Are you not getting proper output on LEDs.
Please clarify further to gain the better insight.
05-21-2018 09:13 AM
What is stored content of address 8'd60 ? Did you performed the behavioral Simulation? Share your project to check at our end.