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Explorer
Explorer
3,884 Views
Registered: ‎03-31-2016

Virtex-7 block ram operation mode simulation issue

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Hello

 

I used the virtex-7 block ram to simulation, but i don't know the simple dual-port ram port A specify no_change mode and write_first mode different.

 

The simulation waveform result is the same.

 

FPGA device: xc7v2000t

 

No_Change mode simulation waveform:

 

No_Change_waveform.PNG

 

Write_first mode simulation waveform:

 

write_first_waveform.PNG

 

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1 Solution

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Moderator
Moderator
7,233 Views
Registered: ‎11-09-2015

Re: Virtex-7 block ram operation mode simulation issue

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Hi @quincyq2003,

 

There is two different things:

-> Simple Dual Port (SDP): "each port is assigned either a read or write functionality" (refer to this video: link). So the portA is configured as write port and the port B as read port.

 

-> Then  Write_first, read_first and No_change are write mode so they applies only on write ports so only on portA. That is the reason why the selection is greyed out for portB. And with 7-series:  "In SDP mode, the WRITE_FIRST mode is automatically mapped to the NO_CHANGE mode for power savings."

 

Hope that helps,

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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5 Replies
Moderator
Moderator
3,866 Views
Registered: ‎11-09-2015

Re: Virtex-7 block ram operation mode simulation issue

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Hi @quincyq2003,

 

You may want to look at UG473 (link). I contains your answer ;-)

memory.JPG

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
3,854 Views
Registered: ‎03-31-2016

Re: Virtex-7 block ram operation mode simulation issue

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Hello @florentw

 

I think this is mean BRAM PORT B only fixed Write_first mode

 

BRAM_PORTB.PNG

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Xilinx Employee
Xilinx Employee
3,849 Views
Registered: ‎08-01-2008

Re: Virtex-7 block ram operation mode simulation issue

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You can also check primitive property in DCP
Thanks and Regards
Balkrishan
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Moderator
Moderator
7,234 Views
Registered: ‎11-09-2015

Re: Virtex-7 block ram operation mode simulation issue

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Hi @quincyq2003,

 

There is two different things:

-> Simple Dual Port (SDP): "each port is assigned either a read or write functionality" (refer to this video: link). So the portA is configured as write port and the port B as read port.

 

-> Then  Write_first, read_first and No_change are write mode so they applies only on write ports so only on portA. That is the reason why the selection is greyed out for portB. And with 7-series:  "In SDP mode, the WRITE_FIRST mode is automatically mapped to the NO_CHANGE mode for power savings."

 

Hope that helps,

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor smattershi
Visitor
2,116 Views
Registered: ‎07-23-2013

Re: Virtex-7 block ram operation mode simulation issue

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nochange.jpg

according to above picture, "if the write port is in WRITE_FIRST or NO_CHANGE mode, data on the output of the read port is invalid". 

But in 

 

 

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