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I am pretty new at FPGA design so I am sorry if I'm asking a rather silly question. I've been playing around in Vivado and I wanted to incorporate the Xilinx Viterbi Decoder IP core into my ZedBoard basic design. But I'm not quite sure how. Should I create a port directly that would be input and output of the decoder? If that is so, I have no use of the other cores in the base design? And I am confused about DSTAT input and output interface, how to connect it. Thank you in advance for help!