07-20-2017 06:41 AM
I have many different experiences using block ram and fifo in xilinx ise and i'm not so newbie in vivado. I have a code developed for clock domain crossing using fifo ip core in vivado 2016.4 and my coding structure was same as previous works treating fifo but there is many strange behaviors hear. After finalizing behavioral simulation and verification of code and implementation without any timing violation, post implementation timing simulation shows fifo output data is only zeroes in each output domain clock cycle(Clock frequency is 250 MHz and related xdc consists of required create_clock timing constraint). After programming this code into the FPGA(kintex7 FPGA with -2 speedgrade), outputs of related block were stable without any dynamic. These steps repeated by disabling implementation optimization. After this new implementation, post implementation simulation was OK and again hardware test failed, unfortunately. Replacing two simple dual port block rams with this fifo shows same problems too. Which considerations are absent hear or which problems with my code can generate these fails?
08-06-2017 07:56 PM
I had the same problems as you!
Last month I used the AXI4-Stream Data FIFO, and the behavior simulation and post-implementation simulation is perfect . Everything seems good. But when I downloaded the bit stream file into the board (ku095), it didn't work! Data was input into the FIFO, but there is no output. And then I changed the stages from 2 to other numbers, but made no sense.
So I abandoned AXI4-Stream data FIFO, alternatively I use FIFO generator to generate a FIFO, so far it works well.
But it remains a question, that is I don't know how to make use of the s_asis_tuser signal. As this FIFO is connected to a MAC, the MAC will assert/de-assert the _tuser signal to inform if the frame received is a good frame or not. And the FIFO is supposed to be able to discard the frame when _tuser signal is de-assert.
Any suggestion will be appreciative. THX