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Visitor cpagravel
Visitor
7,925 Views
Registered: ‎06-15-2016

When does the XILINX AXI BRAM Controller expect valid data from the BRAM?

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I am modifying a project that has a Xilinx AXI BRAM Controller connected to a Xilinx Block Memory Generator. I am removing the Xilinx Block Memory generator and instead I am using a "shared variable" in my code which I am told will be synthesized as BRAM. What I am concerned about is providing the data to the AXI BRAM Controller at an appropriate time after it is requested - since there does not seem to be a data valid signal to indicate that the requested data is being presented. 

 

AXI BRAM Controller.png

 

I have also been told by a co-worker that I should delay the BRAM read cycle by two clocks to ensure I am getting good data. 

 

I.e. this is my code:

 

---------------------------------------
  --MEMORY READ
  ---------------------------------------
  process (sRdClk)
  begin
    if rising_edge(sRdClk) then
      sRdDataReg          <= sRAMblk(conv_integer(sRdPtr));
      sRdData             <= sRdDataReg;
    end if;
  end process;

 

 

The register sRdData is connected to the data output port which goes directly to the AXI BRAM Controller port "brram_rddata_a".

 

For reference, the document for the AXI BRAM Controller is here

The document for the BRAM Generator is here.

 

Is my co-worker correct in suggesting me to code my BRAM interface like this, or will it throw off the AXI BRAM Controller by delivering the data one clock cycle too late?

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Instructor
Instructor
14,594 Views
Registered: ‎08-14-2007

Re: When does the XILINX AXI BRAM Controller expect valid data from the BRAM?

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The BRAM interface is not well documented.  I worked it out using the IP example design.  For that design, the external BRAM was configured without any additional register on the data output port, so it means the controller expects a latency of just one clock cycle, not two as you have coded it.  Also be aware that the BRAM address is a byte address, so you need to throw away the appropriate number of lower bits from the address when using it as a full word address for the BRAM.  If you need more details, the best way is to look through the generated example design in Vivado.

-- Gabor
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Instructor
Instructor
14,595 Views
Registered: ‎08-14-2007

Re: When does the XILINX AXI BRAM Controller expect valid data from the BRAM?

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The BRAM interface is not well documented.  I worked it out using the IP example design.  For that design, the external BRAM was configured without any additional register on the data output port, so it means the controller expects a latency of just one clock cycle, not two as you have coded it.  Also be aware that the BRAM address is a byte address, so you need to throw away the appropriate number of lower bits from the address when using it as a full word address for the BRAM.  If you need more details, the best way is to look through the generated example design in Vivado.

-- Gabor
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Visitor cpagravel
Visitor
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Registered: ‎06-15-2016

Re: When does the XILINX AXI BRAM Controller expect valid data from the BRAM?

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Thanks for that Gabor. I am looking into the example design now and I see what you mean. After looking through this, am I correct in saying that the BRAM_en_A signal (documented as read enable) is asserted when the BRAM is receiving a valid read address? The design I'm working on doesn't actually use that signal from the AXI BRAM Controller and it seems odd that they don't.

 

 

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Instructor
Instructor
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Registered: ‎08-14-2007

Re: When does the XILINX AXI BRAM Controller expect valid data from the BRAM?

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For a single-port interface (port A only), BRAM_en_A will indicate a valid address for either read or write and would connect to the ENA port of the BRAM.  If you use the ENA input of the BRAM, it gates the WEA signal(s) as well as enabling readout of that port.  If you don't hook up the ENA input of the BRAM to the BRAM controller, it should be always active ('1') and then the BRAM port A outputs will update with any address change, while the port A writes will occur any time WEA signal(s) are active.  If the previous design is working correctly, it implies that the AXI BRAM controller never asserts WEA to the BRAM when ENA is inactive.

-- Gabor
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Visitor cpagravel
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Registered: ‎06-15-2016

Re: When does the XILINX AXI BRAM Controller expect valid data from the BRAM?

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Hi Gabor,

 

I have spoken with my colleague and the reason why he suggested to include the additional register is due to the physical device itself. He described to me how there is a register placed on the device which is specifically meant to be used for the BRAM output, otherwise (depending on the clock speeds) it may be difficult to close the timing. Anyway, I'm sure you know all this--I'm a junior developer myself so I'm stating this for my own benefit. 

 

I've looked at the AXI BRAM Controller example and I've noticed there is a delay on the data to the output, so I'm assuming this is why the controller expects the data after a single clock cycle, rather than two. Anyway, I'm going to mark your answer as the solution. Please correct me if I've incorrectly interrupted any of this. 

 

Thanks for the time! 

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Observer nixiebunny
Observer
6,270 Views
Registered: ‎01-26-2009

Re: When does the XILINX AXI BRAM Controller expect valid data from the BRAM?

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@gszakacs wrote:

The BRAM interface is not well documented.  ...the controller expects a latency of just one clock cycle, not two as you have coded it. 


I read through the entire PG078 user guide for this IP block, hoping in vain that there would be some mention of how to configure the BRAM that this block requires to work. No such luck.

 

How do we get the fine folks at Xilinx to actually put this necessary information into the PG078 design guide, so that I don't have to scour the forums looking for information that's supposed to be in the manual?

 

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