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Observer sachinb_apt1
Observer
1,021 Views
Registered: ‎01-03-2018

XPM FIFO wr/rd count incorrect behaviour

I am using a Syncronous XPM FIFO and shocked to see that the rd/wr data count dont change based on every read/write . I issue a rd_en for 3 cycles (with wr_en = 0), i expect to the rd_data_count to change all the 3 cycles, but it doesnt. The document however shows it should every clock cycle. Screenshot attached.

 

The XPM FIFOs really need a re-work Xilinx!

 

SAchin B

rd_wr_count_xpm_fifo.png
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4 Replies
Moderator
Moderator
980 Views
Registered: ‎08-08-2017

Re: XPM FIFO wr/rd count incorrect behaviour

Hi @sachinb_apt1

 

Yes read_data_count should change for every clock cycle.

Please share complete project file or XPM FIFO instantiation to check the attributes settings and reproduce this issue at our end

BRAM.PNG

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If your organization does not allow to share design files in entirety to Public ,You can personally mail me your project or

source file (.v /.vhd) containing XPM FIFO instantiation.

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Reply if you have any queries, give kudos and accept as solution
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Observer sachinb_apt1
Observer
971 Views
Registered: ‎01-03-2018

Re: XPM FIFO wr/rd count incorrect behaviour

Attached are parameters used for xpm fifo. I will see if i can reproduce the issue using a smaller testbench. i used the xilinx xpm fifo testbench available as downloads from userguide. But the issue isnt seen there.

 

fifo params.png
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Observer guerric.mdd
Observer
404 Views
Registered: ‎12-18-2017

Re: XPM FIFO wr/rd count incorrect behaviour

Hello,

I have same problem, using either xpm_fifo_sync or xpm_fifo_async: rd/wr data count are not correct.

I'm using Vivado2017.4 and Fifo in Std mode (not FWFT).

I'll try to post an example soon

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Observer guerric.mdd
Observer
388 Views
Registered: ‎12-18-2017

Re: XPM FIFO wr/rd count incorrect behaviour

Registered: ‎12-18-2017
Re: XPM FIFO wr/rd count incorrect behaviour
 

Here is a very simple test bench.

Basically, simulation (xsim) is not working at all in READ_MODE => "std". Empty stays high while fifo is written !

In READ_MODE => "fwft", simulation is more usable but rd/wr counters are non-sense. Write counter increment every 2 wr_en cycles.

Using logic analyser and implemented design, the "std" mode is in fact working but rd/wr counters are not working in the scenario described in the test bench.

I have no idea about how such basic bugs passed through validation before release...

Is there any Xilinx fix in sight?

Thanks.

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