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Adventurer
Adventurer
511 Views
Registered: ‎04-12-2012

wr_data_count of mixed width XPM FIFO doesn't work

Hello,

 

I'm using an XPM FIFO with a 512 bit write bus and a 128 read bus.

When a single write to the FIFO is performed, I expect "wr_data_count" to increment to 1 and "rd_data_count" to increment to 4...

However, this doesn't happen. Instead, "wr_data_count" stays at 0 while "rd_data_count" rises to 2.

 

A simulation waveform is attached.

Capture.png
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1 Reply
Moderator
Moderator
446 Views
Registered: ‎08-08-2017

Re: wr_data_count of mixed width XPM FIFO doesn't work

Hi @shaikon

 

I hope you have set the attributes properly as given in page 66 of  Libraries user guide. Please verify once.

https://www.origin.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug974-vivado-ultrascale-libraries.pdf

 

I would like to check this behavior at our end. Can you please send us your design ?

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 Note :if your organization does not allowed to share the project in entirety  , Please share the source file where

XPM FIFO is instantiated

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