IP Integrator users connect IP blocks to create complex system designs. These block-based designs are typically constructed at the interface level and interfaces usually contain multiple busses and a large number of individual signals. Therefore, in order to easily debug these designs in hardware, it is necessary to verify the design interface-level connectivity.
The AXI interface debug feature in IP Integrator provides this capability! It allows user to easily monitor and debug both interfaces and signals of a block design by using System ILA IP. The steps involved in using this flow start by identifying the interfaces or nets for debug using the Debug option. This is done by simply right-clicking on the net or interface and selecting Debug from the context menu. This could be an AXI interface or any other interface shown in IP Integrator.
Next Designer Assistance can be used to automatically connect the interfaces and nets to the System ILA IP. Designer Assistance also configures some of the main options for System ILA. Other options, if needed, can be further configured by the user. After the nets have been marked and connected to the System ILA IP, The next step is then to validate the design. This is to make sure that all the nets or interfaces are correctly connected to the System ILA.
After validation, the rest of the flow is seamless as it does not require any extra step. With a click to implement the design or generate bitstream, the user could go all the way through the flow and get to debugging fast. In HW Manager, since interfaces have been preserved through synthesis and implementation they are shown in groups in within the Waveform window. This removes the need for cumbersome interpretation of AXI activities that otherwise require investigation at the signal level for each interface. User can view transaction for multiple AXI interfaces, trigger on events, and capture data at system speeds. In addition, they can enable protocol checking, and other custom options to meet their exact debug needs.
There are many benefits to debug AXI interfaces in IP Integrator! To learn more about this capability, you can look at Programming & Debugging User Guide UG908 and IP Integrator User Guide UG994. You can also watch this Vivado QuickTake video.
In order to further improve this feature, we are also looking for your input via this brief survey. Please take the time to fill it out and let us know your feedback. Your input is valuable to us!
Amir Zeineddini manages the Vivado hardware debug solutions in Xilinx Product Marketing team and has more than 10 years of experience in FPGA design and applications. Since joining Xilinx in 2006, he has held various roles in product marketing, product applications and technical sales. He has also developed a number of application notes and reference designs. Amir highly values customer feedback and is currently focused on augmenting and advancing the debug offerings in Vivado Design Suite.