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umnemezk
Visitor
Visitor
8,992 Views
Registered: ‎09-27-2013

CPLD Damaged - Cause Unknown

Hello,

 

I have been working with a XILINX XCR3256XL CPLD for several weeks now. It was operating successfully until today. During operation, I noticed the voltage regulator on my PCB was hot, and immediately powered everything down. I quickly discovered that the 3.3V power had shorted to ground. I could not find any external shorts on the PCB, so I removed the CPLD from the PCB, and the short circuit no longer existed.

 

This is the only thing that I can think of that was different this time I was working on it: I was using an Agilent signal generator to apply a square wave to five input pins. I believe I accidentally left the signal generator on for a couple minutes after I had removed power from the board during my testing (not when I noticed that there was a problem). Would applying a signal from a device that can drive a significant amount of current when the CPLD is powered down cause the chip to fry? This is my only reasonable guess at the cause of the fault.

 

If anyone could confirm that the chip could be fried this way, that would be great.

 

Thanks.

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austin
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8,982 Views
Registered: ‎02-27-2008

u,

 

Exceding the absolute maximum ratings for voltage, or current may cause failure.  ESD may cause failure if it is freater that the limits stated in the data sheets and ug116.pdf report.

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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umnemezk
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8,974 Views
Registered: ‎09-27-2013

I don't believe I exceeded the maximum rating for the chip while it was powered on. My question is what happens when the chip is powered down and levels are applied at near the maximums? Is there a change in impedance when the chip is off that could lead to excess current input?

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austin
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Registered: ‎02-27-2008

Yes,


An example would be that in trying to power the CPLD through its IO pins results in also trying to power on all the loads connected to that IO bank power suppy (all the other devices).  That would take perhaps something more than 200 mA, which potentially might cause an issue.


The IO bank failed in the shorted condition, it is much more likely that you zapped it with ESD.


Were you using a grounded worktable, Was all equipment grounded to the same safe ground?  Was the board itself also grounded safely to the bench ground?

 

Were you wearing an ESD wrist or ankle strap?

 

Were you wearing synthetic (rayon, nylon, etc.) clothing?

 

Are you in a cold climate with indoor heat and low humidity?

 

I know of some signal generators which can go up to 20 volts, and more, so how sure are you your signal generator was not set to a higher voltage output?

 

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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umnemezk
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8,955 Views
Registered: ‎09-27-2013

The grounding at the workstation is quite good. I usually wear a wrist strap, and am fairly sure that I was at the time of failure, but I don't remember for sure.

 

I am in a cold climate with low humidity and indoor heat.

 

I tested the signal generator output with an oscilloscope before applying it to the CPLD.

 

Bascially, I want to verify that the cause of the fault was due to testing, and not some core design flaw. I don't want to order more parts with every one doomed to fail eventually. I'm suspecting there isn't a core flaw because of the previous successful operation.

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austin
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8,948 Views
Registered: ‎02-27-2008

u,

 

If the design has no design rule check violations you forced to be warnings (something you would know you did, as a DRC error will not result in a programmable design file), then there is nothing you can do to destroy the part.  Nothing.

 

Destruction is greater than absolute maximum voltage or current applied, ESD, or junction temperature (greatly) excedes the maximum.

 

Again, there is nothing you can (legally) program that would cause a part to fail.

Austin Lesea
Principal Engineer
Xilinx San Jose
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chris_basson
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Registered: ‎10-27-2009

Just a shot in the dark. I notice most of the advice focus on possible ESD damage. Another meganism which may damage your chip is by applying signal levels to the device IO-pins before power is applied and then bring up power. This could cause destructive latch-up of device IO.

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austin
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8,907 Views
Registered: ‎02-27-2008

Latch-up of IOs is specified,

 

It takes in excess of 200 mA injected into the part to even try to cause latch-up.

 

Generally speaking, latch-up (with anything less than 200 mA) is a sign of a poorly designed part.  In Xilinx history we only had one part subject to latch-up:  the Coolrunner part when it was first purchased (from another company).  We re-engineered it, and re-released it, without latch-up, or latch-up potential beyond 200 mA.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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