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Anonymous
Not applicable
4,171 Views

IO PIN status Test with Boundary Scan!!!?

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Hi there

if you work with some of DSPs or MicroProcessors, you know you could check GPIO status by Boundary scan via JTAG Interface.

So my question is that is it possible to do the same with XC9500XL CPLD Families via their JTAG interface? if its possible HOW can I do it?

Tangs 4 help (^_^)

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Xilinx Employee
Xilinx Employee
4,959 Views
Registered: ‎07-30-2007

Yes this is absolutely possible in the hardware.

However Xilinx does not provide software to implement this boundary scan testing. Xilinx does provide boundary scan files for all of their devices (BSDL files). You need to find a 3rd party tool that will load in these BSDL files and then can drive your JTAG pins on your board to do the testing you desire.

 

/Arthur

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Anonymous
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It seems that there are no suggestions here :-(

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Xilinx Employee
Xilinx Employee
4,960 Views
Registered: ‎07-30-2007

Yes this is absolutely possible in the hardware.

However Xilinx does not provide software to implement this boundary scan testing. Xilinx does provide boundary scan files for all of their devices (BSDL files). You need to find a 3rd party tool that will load in these BSDL files and then can drive your JTAG pins on your board to do the testing you desire.

 

/Arthur

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