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gerard.spivey
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Registered: ‎06-28-2011

Minimum Clock Frequency for CoolRunner 2 CPLD

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I would like to know if I can run the Devices in the CoolRunner 2 CPLD family within the 100Hz range. I have seen a similar thread http://forums.xilinx.com/t5/CPLDs/Minimum-Frequecny-input-for-CPLD-XC95288XL/m-p/27690#M832 that seems to state that this could be possible, but there are mentions to slew rate & rise/fall time considerations.

 

Does this mean I can run such a slow clock but it would need very fast rising edges, and if so what would be the minimum rise time allowed by such a slow clock?

 

Thanks in Advanced

 

Gerard

 

 

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austin
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Registered: ‎02-27-2008
gerard,

0 Hz: all static, basically as slow as you like.

The rise and fall times of slow clocks need to be "normal" (a sine wave is highly discouraged, as a slow rise time may lead to glitches causing multiple clocks on an edge, so if you have any normal logic generating a clock, like a CMOS divider IC, then it will work just fine -- that was the warning in the thread you refer to).

"Normal" rise and fall times are in the single digit nanoseconds range: what you get from most CMOS logic devices, and clock generators.

Austin Lesea
Principal Engineer
Xilinx San Jose

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eteam00
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Registered: ‎07-21-2009

The answers are provided in the thread you linked, and in one of the referenced Answer Records.

 

See Answer Record 3226.

 

-- Bob Elkind

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gerard.spivey
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Bob,

 

Thanks for quick response.

 

Unless I am missing something in that link there are only statements for maximum rise times, no minimum rise times. "The recommended maximum rise/fall times for any input is 20 nS" (For CoolRunner 2).

 

Therefore my post was to verify I understood the original thread correctly that "there is no minimum clock frequency" ie 100Hz is no issue.

 

Secondly since there was mention of rise/fall time concerns explicit maximums were stated but no minimum were stated therefore what are the minimum requirements or where can I find the minimum requirements.

 

Thanks

 

Gerard

 

 

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eteam00
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Registered: ‎07-21-2009

Unless I am missing something in that link there are only statements for maximum rise times, no minimum rise times. "The recommended maximum rise/fall times for any input is 20 nS" (For CoolRunner 2).

 

Why should there be a minimum risetime spec?  Do you have any reason to believe that an edge which switches from '0' to '1' can be so fast that it is too fast?  This isn't the sort of concern one usually associates with a '100Hz' clock frequency design.

 

Secondly since there was mention of rise/fall time concerns explicit maximums were stated but no minimum were stated therefore what are the minimum requirements or where can I find the minimum requirements.

 

Minimum and maximum risetimes are two completely different problems.  You should not expect that a maximum risetime specification requires a corresponding minimum risetime specification.

 

A maximum risetime spec addresses the problem of a logic input signal 'hovering' at the input logic switching threshold, where noise might cause oscillation (particularly unfortunate for clock signals) and where FETs might be operating in a high-current condition (and power dissipation and heating would persist and lead to device failure).

 

It could well be (speculation on my part) that the device package inductance and capacitance represents a low-pass filter for input signals, to the extent that even a theoretical '0pS' instantaneously switching input signal would not present a problem.

 

As explicitly stated in the thread to which you originally linked, there is no minimum clock frequency for Xilinx CPLDs.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
drjohnsmith
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Registered: ‎07-09-2009

cpld has no dll / pll, and can run static,

    as slow as you like.

 

how fast an edge, 

    just about any logic gate will do , provided it meats voltage levels.

 

 

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austin
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Registered: ‎02-27-2008
gerard,

0 Hz: all static, basically as slow as you like.

The rise and fall times of slow clocks need to be "normal" (a sine wave is highly discouraged, as a slow rise time may lead to glitches causing multiple clocks on an edge, so if you have any normal logic generating a clock, like a CMOS divider IC, then it will work just fine -- that was the warning in the thread you refer to).

"Normal" rise and fall times are in the single digit nanoseconds range: what you get from most CMOS logic devices, and clock generators.

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

gerard.spivey
Newbie
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9,247 Views
Registered: ‎06-28-2011

All,

 

 

Thanks for your time and help, all is clear now.

 

 

Gerard

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