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Visitor cristianalex
Visitor
7,165 Views
Registered: ‎08-01-2011

Problem with programming XC95144XL

I am trying to program a XC95144XL CPLD and I have problems uploading the code in the device.

What I can tell you about the hardware I use:

- Digilent HS1 Jtag - USB cable

- The cpld is not connected to any development board we use a test bench to asses the device

- All VCC int pins are connected to 3.3V

- All VCC I/O pins are connected to 3.3V

- All ground pins are connected

 

This is what I've tried so far:

- uploading different programs, same result

- using a different cpld chip, same result

- verifying if there is any communication on the jtag cable on TDI and TDO pins, result was ok

- using the digilent adept software to upload a svf file made with impact, it says that the operation ends successful but the device does nothing.

 

I've uploaded an iMPACT log with the error I get when I try to program the device.

 

 

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5 Replies
Scholar austin
Scholar
7,156 Views
Registered: ‎02-27-2008

Re: Problem with programming XC95144XL

c,

Check the signal integrity of the JTAG signals. Look at them with an oscilloscope. It looks like for short JTAG communications, the operations succeeded (erasing the device), but when it tried to program, it failed.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor cristianalex
Visitor
7,148 Views
Registered: ‎08-01-2011

Re: Problem with programming XC95144XL

I've did that, the signals remain constant between 3.1 V and 3.5 V for high logic and 0 at low.

 

I don't know if the short communication hypothesis is good because the readback process ends successfully and it's fairly long. (I don;t really know what's the procedure behind it and if I have loss of signals on the Jtag cable if they are substituted for 0 for the readback process)

 

Anyway the problem in the programming process seams to be random in some sort because I have times when it stops (just like a kill signal is generated) at 0% and the device is blank if I do a blank check or at 15%, 7%, 32% (random numbers) and if I do a readback from the board the .jed file generated matches for a while with that I want to write. And this happens on both boards that we've developed. (you can see an example of that in the files I've attached)

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Teacher eteam00
Teacher
7,143 Views
Registered: ‎07-21-2009

Re: Problem with programming XC95144XL

I've did that, the signals remain constant between 3.1 V and 3.5 V for high logic and 0 at low.

 

For signal integrity concerns, the important aspects of the signals include edge shapes -- and not just signal levels.  Of paticular interest are the TCK signal edges, both rising and falling.

 

Are the logic level transitions free of flat spots and mid-transition direction reversals?

 

Once the new logic level is reached, does the waveform maintain that level without ringing incursions into the switching region?

 

-- Bob Elkind

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Visitor cristianalex
Visitor
7,140 Views
Registered: ‎08-01-2011

Re: Problem with programming XC95144XL

 

I've checked TCK, TDI, TDO  signals. Edges are good, after reaching a new level the waveform maintains a constant level without interference, logic levels are within parameters, everything seams to be good. (I don't have any capture now to post it but the signals look just like they should do)

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Observer satish.84ts
Observer
6,651 Views
Registered: ‎10-21-2012

Re: Problem with programming virtex-5 fpga having cpld chain

I have jtag chain with cpld followed by virtex-5 fpga.I want to program virtex-5 fpga using impact(14.2),i ceated chipscope core inserter and i dump the .bit file into the virtex-5 fpga by bypassing the cpld.But after doing this thing i am not able to load the .bit file into virtex-5 fpga using usb cable from c-language.My cpld is programed with the "comport-3 communication and control".Now i am getting problem to load .bit file into fpga using usb cable in c-language,the usb cable is communicating with the comport-3 through pc.At last what is my problem is i did program in the fpga and is there any cahnce to erase the cpld content which is having comport-3 program.I bypassed the cpld when i am programing the fpga.Please help me out....urgent............

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