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Question on using Coolrunner-II CPLD (I/O and counter)

I'm a newbie in using CPLD. I'm now working on projects and desided to move all the logics of my original circuit into a single CPLD, and draw the schematic in ISE.

I have a Coolrunner-II starter kit and my schematic works well on it.


Problems come when I try to contruct my own circuit. I implement my schematic on a XC2C128. The problem is all IO belongs I/O Bank 1 show nothing while those belong I/O Bank 2 work well. Originally I thought it might be the problem of my PCB circuit and I made another PCB and placed a new XC2C128 on it. The same problem appeared.


Another problem is that some of the counters (blocks provided in ISE) don't work. I use counter to generate several synchronized clocks of different frequency. I found some counters works as what I designed and some didn't. What could the problem be. (The same problem didn't happen on my Coolrunner-II starter kit...the same schematic file works very fine there)


I found there are some control pins on the CPLD (GTS, CDRST, GSR...etc). I found most of them just simply treated as I/O on my Coolrunner-II starter kit. But on the kit, I realize there is a microcontroller. I think it is for programming the CPLD. Are there any other function of that MCU? Does a CPLD need some initialization before it can work properly?



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Xilinx Employee
Xilinx Employee
Registered: ‎07-30-2007

The CPLD does not require any external hardware to initialize it upon powerup. The microcontroller is there to manage the USB data and configure the CPLD. I assume you use JTAG to  configure the CPLD on your new board, so you have the JTAG pins pulled out to a header that you can connect a programming cable to.


If the logic works properly on your demoboard, but not on your PCB, it seems to indicate a problem with your board, and not the code. Also since it works in one bank and not in antoher also indicates a problem with your board. Check the pinout in the report file to ensure that you have the pins locked to the right places. Also check the board layout to ensure that you have proper Vccio and GND. Also check for shorts in between adjacent pins. 


Here is an appnote that helps with some guidelines for doing a CPLD design:



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Thanks for your reply. I have checked all the pin and verified that no pins are shorted. Also, all the Vccio and Vaux are connected to 3.3V and Vcc to 1.8V. All ground are connected. Power is supplied by batteries (I'm sure it can provide enough current) and regulated by 2 linear regulator.


My circuit is a simple one, just with several I/O pins connected to headers for measurement. All Vcc, Vccio and Vaux have small decoupling capacitors connected next to it.


Till now, all problems are still the same.


Thank you.

Message Edited by chostephen on 03-21-2009 01:34 AM
Message Edited by chostephen on 03-21-2009 01:41 AM
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