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11,496 Views
Registered: ‎09-12-2007

Really Slow Clock

Hello,

We have a 32 macrocell coolrunner II project where we need a very very slow clock (about 40 Hz). We thought we had an easy solution. We just used an RC filer, where we set the input to have a schmitt trigger. The input signal was inverted and sent to an output pin. The output pin charges the 0.1uF cap through a 152K resistor.

It all seemed simple enough (and it works), but when we look at the power consumption, it appears to be taking around 2mA! What is going on? If we disconnect the oscillator and just use a function generator of the same frequency into the input pin, the power usage is multiples less (provided I lift the output pin).

I realize there are other circuits on the net, but I am mostly curious why mine is consuming so much power.

The design is basically used to run a timer for 15 minutes, and when the time is up, disable components on a board that consume a lot of power. A button resets the timer. There are also LEDs and things that blink on occasion, but you get the picture.

We have keeper globally enabled, with the clock input pin set to FLOAT, because otherwise the 100K pullup voltage device with the 152K resistor, so the capacitor voltage never reaches the threshold.

Thanks for you help!
Ben
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3 Replies
Explorer
Explorer
11,487 Views
Registered: ‎08-13-2007

Re: Really Slow Clock

when you apply external clock the the CPLD is fully in "digital domain"
however with the R-C oscillator the input cell is part time in "linear (analog) domain" as the input voltage is changing slowly hence the power consumption increase.
 
its no so easy to design a very low power oscillator :)
 
once I made a design that flashes a LED once a minute for YEARS from single battery, it wasnt so easy to get the power down (not it was not cpld based)
 
Antti
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Highlighted
11,398 Views
Registered: ‎09-12-2007

Re: Really Slow Clock

I realized that the RC filter was analog...that was why I added the schmitt trigger.
 
Can someone at least explain to me where that power is going?
 
Even if the capacitor was totally discharged, and the inverted clock output was 3.3V, that is only 3.3V/152K = 22uA.  And this current would probably never flow, because the capacitor would never totally discharge.  It would just hit the downgoing threshold for the schmitt trigger. 
 
For the input, correct me if I am wrong, but the input transistors shouldn't be sitting in linear mode because of the schmitt trigger.  This should cause them to have a firm, digital switch from high to low impedance.
 
How am I getting 2mA loss when this pin is connected?
 
Thanks,
Ben
 
PS:  There are underlying business reasons a micropower microcontroller wasn't used for this design.  I am aware that this might be the easiest way.  Is there another way to get a very slow clock?  (Remember, I only have 32 macrocells for everything, so I can't divide down too high of a clock)
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Explorer
Explorer
11,383 Views
Registered: ‎08-13-2007

Re: Really Slow Clock

Hi
 
the schmit trigger input option does not mean the input will work as digital one when you apply voltage in linear range. it only will turn on input hysteresis.
 
so while the voltage "ramps" in the input, it will defenetly be long time in linear region, no matter the input buffer io standard selection.
 
you are trying to oversmart the technology :(
 
so you may end up using a mcu, some external to CPLD solution or maybe POWR607 device ;)
 
Antti
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